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ORCIDASAP 2010: Rennes, France
- François Charot, Frank Hannig, Jürgen Teich, Christophe Wolinski:
21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010. IEEE Computer Society 2010, ISBN 978-1-4244-6967-3
Keynotes
- Ahmed Amine Jerraya:
Convergence of design and fabrication technologies, a key enabler for HW-SW integration. 3 - Sani R. Nassif:
The light at the end of the CMOS tunnel. 4-9
Mapping for Multi-Core Architectures
- Seung Chul Jung, Aviral Shrivastava
, Ke Bai:
Dynamic code mapping for limited local memory systems. 13-20 - Weijia Che, Karam S. Chatha:
Design of an Automatic Target Recognition algorithm on the IBM Cell Broadband Engine. 21-28 - Keisuke Dohi, Khaled Benkrid, Cheng Ling, Tsuyoshi Hamada, Yuichiro Shibata:
Highly efficient mapping of the Smith-Waterman algorithm on CUDA-compatible GPUs. 29-36
Design Space Exploration
- Dhara Dave, Christos Strydis, Georgi Gaydadjiev:
ImpEDE: A multidimensional design-space exploration framework for biomedical-implant processors. 39-46 - Adrien Le Masle, Wayne Luk:
Design space exploration of parametric pipelined designs. 47-54 - Tung Thanh Hoang, Ulf Jalmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Själander, Per Larsson-Edefors:
Design space exploration for an embedded processor with flexible datapath interconnect. 55-62
Systems-On-Chip and Networks-On-Chip
- Tobias Beisel, Manuel Niekamp, Christian Plessl:
Using shared library interposing for transparent application acceleration in systems with heterogeneous hardware accelerators. 65-72 - Sujay Deb, Amlan Ganguly, Kevin Chang, Partha Pratim Pande, Benjamin Belzer, Deuk Hyoun Heo:
Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects. 73-80 - Amelia W. Azman, Abbas Bigdeli, Yasir Mohd-Mustafah, Morteza Biglari-Abhari, Brian C. Lovell:
A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design. 81-88 - Turbo Majumder, Souradip Sarkar, Partha Pratim Pande, Ananth Kalyanaraman:
An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem. 89-96
Formal Methods
- Heng Kuang, Olga Ormandjieva, Stan Klasa, Jamal Bentahar:
A formal specification of fault-tolerance in prospecting asteroid mission with Reactive Autonomie Systems Framework. 99-106 - Yocheved Dotan, Orgad Chen, Gil Katz:
Comparing the robustness of fault-tolerant enhancements when applied to lookup tables and random logic for nano-computing. 107-114 - Gaetan Canivet, Paolo Maistri, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin:
Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA. 115-122
Design and Programming of Array Architectures
- Hritam Dutta, Frank Hannig, Moritz Schmid, Joachim Keinert:
Modeling and synthesis of communication subsystems for loop accelerator pipelines. 125-132 - Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain:
Design of throughput-optimized arrays from recurrence abstractions. 133-140 - Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit:
A C++-embedded Domain-Specific Language for programming the MORA soft processor array. 141-148
Application-Specific Processors
- Guillermo Payá Vayá, Javier Martín-Langerwerf, Holger Blume, Peter Pirsch:
A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures. 151-158 - Mehdi Kamal, Neda Kazemian Amiri, Arezoo Kamran, Seyyed Alireza Hoseini, Masoud Dehyadegari, Hamid Noori:
Dual-purpose custom instruction identification algorithm based on Particle Swarm Optimization. 159-166 - Antoine Floch, Christophe Wolinski, Krzysztof Kuchcinski:
Combined scheduling and instruction selection for processors with reconfigurable cell fabric. 167-174 - Florian Brandner:
Completeness of automatically generated instruction selectors. 175-182
Computer Arithmetics and Cryptography
- Ünal Koçabas, Junfeng Fan, Ingrid Verbauwhede:
Implementation of binary edwards curves for very-constrained devices. 185-191 - Samuel Antao, Jean-Claude Bajard, Leonel Sousa:
Elliptic Curve point multiplication on GPUs. 192-199 - Nicolas Louvet, Jean-Michel Muller, Adrien Panhaleux:
Newton-Raphson algorithms for floating-point division using an FMA. 200-207 - David B. Thomas, Wayne Luk:
An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers. 208-215 - Florent de Dinechin, Mioara Joldes, Bogdan Pasca:
Automatic generation of polynomial-based hardware architectures for function evaluation. 216-222
Application-Specific Architectures
- Bo Xiang, Dan Bao, Shuangqu Huang, Xiaoyang Zeng:
A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications. 225-232 - Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Fumiaki Maehara, Satoshi Goto:
High parallel variation Banyan network based permutation network for reconfigurable LDPC decoder. 233-238 - Chunshu Li, Kai Huang, Xiaolang Yan, Jiong Feng, De Ma, Haitong Ge:
A high efficient memory architecture for H.264/AVC motion compensation. 239-245 - Kazuya Katahira, Kentaro Sano, Satoru Yamamoto:
FPGA-based lossless compressors of floating-point data streams to enhance memory bandwidth. 246-253
Power-Aware Architectures
- Wei Liu, Alberto Nannarelli:
Power dissipation challenges in multicore floating-point units. 257-264 - Shaoshan Liu, Richard Neil Pittman, Alessandro Form, Jean-Luc Gaudiot:
On energy efficiency of reconfigurable systems with run-time partial reconfiguration. 265-272 - Xin Fan, Milos Krstic, Christoph Wolf, Eckhard Grass:
A GALS FFT processor with clock modulation for low-EMI applications. 273-278
Posters
- Jie Tang, Shaoshan Liu, Zhimin Gu, Xiao-Feng Li, Jean-Luc Gaudiot:
Hardware-assisted middleware: Acceleration of garbage collection operations. 281-284 - Mohamed N. Hassan, Mohammed Benaissa, Anastasios Kanakis:
Flexible hardware/software co-design for scalable elliptic curve cryptography for low-resource applications. 285-288 - Oguzhan Atak, Abdullah Atalar:
An efficient computation model for coarse grained reconfigurable architectures and its applications to a reconfigurable computer. 289-292 - Emrah Tasdemir, Götz Kappen, Tobias G. Noll:
Potential of using block floating point arithmetic in ASIP-based GNSS-receivers. 293-296 - Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese:
Area optimized H.264 Intra prediction architecture for 1080p HD resolution. 297-300 - Kazeem Alagbe Gbolagade, George Razvan Voicu, Sorin Dan Cotofana:
Memoryless RNS-to-binary converters for the {2n+1 - 1, 2n, 2n - 1} moduli set. 301-304 - Elif Bilge Kavun, Tolga Yalçin:
A pipelined camellia architecture for compact hardware implementation. 305-308 - Jakub Szefer, Yu-Yuan Chen, Ruby B. Lee:
General-purpose FPGA platform for efficient encryption and hashing. 309-312 - Jo Vliegen, Nele Mentens, Jan Genoe, An Braeken, Serge Kubera, Abdellah Touhafi, Ingrid Verbauwhede:
A compact FPGA-based architecture for elliptic curve cryptography over prime fields. 313-316 - Nicolas Brisebarre, Nicolas Louvet, Érik Martin-Dorel, Jean-Michel Muller, Adrien Panhaleux, Milos D. Ercegovac:
Implementing decimal floating-point arithmetic through binary: Some suggestions. 317-320 - Maisam Mansub Bassiri, Hadi Shahriar Shahhoseini:
A New approach in on-line task scheduling for reconfigurable computing systems. 321-324 - Stephen Wray, Wayne Luk, Peter R. Pietzuch:
Exploring algorithmic trading in reconfigurable hardware. 325-328 - Christophe Alias, Alain Darte, Alexandru Plesco:
Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool. 329-332 - Peng Li, Kunal Agrawal, Jeremy Buhler, Roger D. Chamberlain, Joseph M. Lancaster:
Deadlock-avoidance for streaming applications with split-join structure: Two case studies. 333-336 - Jian Li, David Dickin, Lesley Shannon:
Customizing controller instruction sets for application-specific architectures. 337-340 - Jonathan Piat, Shuvra S. Bhattacharyya, Mickaël Raulet:
Loop transformations for interface-based hierarchies IN SDF graphs. 341-344 - Raymond Manley, Paul Magrath, David Gregg:
Code generation for hardware accelerated AES. 345-348 - Xun Li, Mohit Tiwari, Timothy Sherwood, Frederic T. Chong:
Function flattening for lease-based, information-leak-free systems. 349-352
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