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ORCIDASAP 2011: Santa Monica, CA, USA
- Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca:
22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1291-3 - Message from the conference chairs.
Keynotes
- Jason Cong:
Era of customization and specialization. 3 - Michael J. Flynn:
More than 50 years of parallel processing and still no easy path to speedup. 4 - Viktor K. Prasanna:
Architectures for Green routers. 5
Session 1: Reconfigurable Systems
- Stewart Denholm, Kuen Hung Tsoi, Peter R. Pietzuch
, Wayne Luk:
CusComNet: A customisable network for reconfigurable heterogeneous clusters. 9-16 - Muhammad Ali Shami, Ahmed Hemani:
Address generation scheme for a coarse grain reconfigurable architecture. 17-24 - Jason Cong, Beayna Grigorian, Glenn Reinman, Marco Vitanza:
Accelerating vision and navigation applications on a customizable platform. 25-32
Session 2: Computer Arithmetic and Algorithms
- Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn:
A high-performance, low-power linear algebra core. 35-42 - Ahmet Akkas, Michael J. Schulte:
A decimal floating-point fused multiply-add unit with a novel decimal leading-zero anticipator. 43-50 - Ioannis Sourdis, Sri Harsha Katamaneni:
Longest Prefix Match and updates in Range Tries. 51-58
Session 3: System Profiling
- Mark Aldham, Jason Helge Anderson, Stephen Dean Brown, Andrew Canis:
Low-cost hardware profiling of run-time and energy in FPGA embedded processors. 61-68 - Joseph M. Lancaster, E. F. Berkley Shands, Jeremy D. Buhler, Roger D. Chamberlain:
TimeTrial: A low-impact performance profiler for streaming data applications. 69-76
Session 4: MultiCore Processors and Networks
- Luigi Pomante:
System-level design space exploration for dedicated heterogeneous multi-processor systems. 79-86 - Vahid Lari, Andriy Narovlyanskyy, Frank Hannig, Jürgen Teich:
Decentralized dynamic resource management support for massively parallel processor arrays. 87-94 - Oguzhan Erdem, Hoang Le, Viktor K. Prasanna, Cüneyt F. Bazlamaçci:
Hybrid data structure for IP lookup in virtual routers using FPGAs. 95-102
Session 5: Communication Systems
- Changsheng Zhou, Yunlong Ge, Xubin Chen, Yun Chen, Xiaoyang Zeng:
An area-Efficient LDPC decoder for multi-standard with conflict resolution. 105-112 - Guohui Wang, Yang Sun, Joseph R. Cavallaro, Yuanbin Guo:
High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder. 113-121 - Syed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte:
Energy-efficient floating-point arithmetic for software-defined radio architectures. 122-129
Session 6: GPUs and Accelerators
- Samuel Neves, Filipe Araújo:
On the performance of GPU public-key cryptography. 133-140 - Alessandro Strano, Davide Bertozzi, Arnaud Grasset, Sami Yehia:
Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration. 141-148 - Shawn Singh, Seung hyun Pan, Milos D. Ercegovac:
Accelerating the photon mapping algorithm and its hardware implementation. 149-157
Session 7: Image Processing
- Peng Li, David J. Lilja:
A low power fault-tolerance architecture for the kernel density estimation based image segmentation algorithm. 161-168 - Christian Banz, Carsten Dolar, Fabian Cholewa, Holger Blume:
Instruction set extension for high throughput disparity estimation in stereo image processing. 169-175 - Yunus Emre, Chaitali Chakrabarti:
Low energy motion estimation via selective aproximations. 176-183
Session 8: FPGA Applications
- Florent de Dinechin, Jean-Michel Muller, Bogdan Pasca, Alexandru Plesco:
An FPGA architecture for solving the Table Maker's Dilemma. 187-194 - Oliver Knodel, Thomas B. Preußer, Rainer G. Spallek:
Next-generation massively parallel short-read mapping on FPGAs. 195-201 - Rodolfo Redlich, Gonzalo Carvajal, Miguel E. Figueroa:
An FPGA-based real-time nonuniformity correction system for Infrared Focal Plane Arrays. 202-208
Posters
- Chenglong Xiao, Emmanuel Casseau:
Efficient custom instruction enumeration for extensible processors. 211-214 - Razvan Nane, Sven van Haastregt, Todor P. Stefanov, Bart Kienhuis, Vlad Mihai Sima, Koen Bertels:
IP-XACT extensions for Reconfigurable Computing. 215-218 - Abelardo Jara-Berrocal, Ann Gordon-Ross:
An integrated development toolset and implementation methodology for partially reconfigurable system-on-chips. 219-222 - Tobias Beisel, Tobias Wiersema, Christian Plessl, André Brinkmann:
Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. 223-226 - Shobana Padmanabhan, Yixin Chen, Roger D. Chamberlain:
Optimal design-space exploration of streaming applications. 227-230 - Ke Bai, Aviral Shrivastava, Saleel Kudchadker:
Stack data management for Limited Local Memory (LLM) multi-core processors. 231-234 - Zheng Zhou, Gang Qu:
An energy efficient adaptive event detection scheme for wireless sensor network. 235-238 - Tomás Martínek, Matej Lexa:
Architecture model for approximate tandem repeat detection. 239-242 - Marko Miklo, Carl R. Elks, Ronald D. Williams:
Design of a high performance FPGA based fault injector for real-time safety-critical systems. 243-246 - Jason Cong, Karthik Gururaj, Muhuan Huang, Sen Li, Bingjun Xiao, Yi Zou:
Domain-specific processor with 3D integration for medical image processing. 247-250 - João Carlos Néto, Alexandre F. Tenca, Wilson Vicente Ruggiero:
A parallel k-partition method to perform Montgomery Multiplication. 251-254 - Mark G. Arnold, Ioannis Kouretas, Vassilis Paliouras:
A Residue Logarithmic Number System ALU using interpolation and cotransformation. 255-258 - Yanjie Peng, Kai Zhang, Andrew G. Klein, Xinming Huang:
Design and implementation of a belief propagation detector for sparse channels. 259-262
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