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ORCIDASAP 2012: Delft, The Netherlands
- 23rd IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2012, Delft, The Netherlands, July 9-11, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-2243-0
Reconfigurable Logic and Graphics Engines
- Hau T. Ngo, Jennifer Shafer, Robert W. Ives, Ryan N. Rakvic, Randy P. Broussard:
Real Time Iris Segmentation on FPGA. 1-7 - Brahim Betkaoui, Yu Wang
, David B. Thomas, Wayne Luk:
A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration. 8-15 - Roto Le, Joseph L. Mundy, R. Iris Bahar:
High Performance Parallel JPEG2000 Streaming Decoder Using GPGPU-CPU Heterogeneous System. 16-23 - Lin Ma, Roger D. Chamberlain:
A Performance Model for Memory Bandwidth Constrained Applications on Graphics Engines. 24-31
Special Session on Ongoing EU Projects
- Koen Bertels:
EU Collaborative Research on Application-Specific Systems. 32-45
Advances in Arithmetic
- Nicolas Brisebarre, Milos D. Ercegovac, Jean-Michel Muller:
(M, p, k)-Friendly Points: A Table-Based Method for Trigonometric Function Evaluation. 46-52 - Carlos Garcia-Vega, Sonia González-Navarro, Julio Villalba-Moreno, Emilio L. Zapata:
On-line Decimal Adder with RBCD Representation. 53-60 - Syed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte:
Virtual Floating-Point Units for Low-Power Embedded Processors. 61-68 - Claude-Pierre Jeannerod, Jingyan Jourdan-Lu:
Simultaneous Floating-Point Sine and Cosine for VLIW Integer Processors. 69-76
Digital Signal Processing Applications
- Jeffrey R. Johnston, Rob A. Rutenbar:
A High-Rate, Low-Power, ASIC Speech Decoder Using Finite State Transducers. 77-85 - George F. Zaki, William Plishker, Shuvra S. Bhattacharyya, Frank Fruth:
Partial Expansion Graphs: Exposing Parallelism and Dynamic Scheduling Opportunities for DSP Applications. 86-93 - Alejandro Nieto, David López Vilariño, Víctor M. Brea:
SIMD/MIMD Dynamically-Reconfigurable Architecture for High-Performance Embedded Vision Systems. 94-101
Cryptology and Security
- Santosh Ghosh, Jeroen Delvaux, Leif Uhsadel, Ingrid Verbauwhede:
A Speed Area Optimized Embedded Co-processor for McEliece Cryptosystem. 102-108 - Leif Uhsadel, Markus Ullrich, Ingrid Verbauwhede, Bart Preneel:
Interface Design for Mapping a Variety of RSA Exponentiation Algorithms on a HW/SW Co-design Platform. 109-116 - Jeremy Constantin, Andreas Burg, Frank K. Gürkaynak:
Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture. 117-124
Application-Specific Acceleration
- Qiuling Zhu, Kaushik Vaidyanathan, Ofer Shacham, Mark Horowitz, Larry T. Pileggi, Franz Franchetti:
Design Automation Framework for Application-Specific Logic-in-Memory Blocks. 125-132 - Muhammad Waqar Azhar, Magnus Själander, Hasan Ali, Akshay Vijayashekar, Tung Thanh Hoang, Kashan Khurshid Ansari, Per Larsson-Edefors:
Viterbi Accelerator for Embedded Processor Datapaths. 133-140 - Libo Huang, Zhiying Wang, Nong Xiao:
Accelerating NoC-Based MPI Primitives via Communication Architecture Customization. 141-148
Posters
- Ardavan Pedram, Syed Zohaib Gilani, Nam Sung Kim, Robert A. van de Geijn, Michael J. Schulte, Andreas Gerstlauer:
A Linear Algebra Core Design for Efficient Level-3 BLAS. 149-152 - Mehdi Modarressi, Hamid Sarbazi-Azad:
Reconfigurable Cluster-Based Networks-on-Chip for Application-Specific MPSoCs. 153-156 - Nikolaos Kavvadias, Kostas Masselos:
Automated Synthesis of FSMD-Based Accelerators for Hardware Compilation. 157-160 - Pedro Martín, Osmell Machado, Francisco J. Rodríguez, Emilio José Bueno:
Design Space Exploration for the Implementation of a Predictive Current Controller Based on FPGA. 161-164 - Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Jürgen Teich:
Design of Low Power On-chip Processor Arrays. 165-168 - Stephen McKeown, Roger F. Woods:
Novel Application of Genetic Sequencing Algorithms to Optimization of Hardware Resource Sharing for DSP. 169-172 - Sven van Haastregt, Bart Kienhuis:
Enabling Automatic Pipeline Utilization Improvement in Polyhedral Process Network Implementations. 173-176 - Michael B. Sullivan, Earl E. Swartzlander Jr.:
Long Residue Checking for Adders. 177-180 - H. Fatih Ugurdag, Ali Basaran, Taylan Akdogan, V. Ugur Güney, Sezer Gören:
FPGA Based Particle Identification in High Energy Physics Experiments. 181-184 - Tim Todman, Wayne Luk:
Reconfigurable Design Automation by High-Level Exploration. 185-188
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