ASP-DAC 2011: Yokohama, Japan

• Ying-Chih Wang, Anvesh Komuravelli, Paolo Zuliani, Edmund M. Clarke:
  Analog circuit verification by statistical model checking. 1-6
  
• Chenjie Gu, Jaijeet S. Roychowdhury:
  FSM model abstraction for analog/mixed-signal circuits by learning from I/O trajectories. 7-12
  
• Xuexin Liu, Hao Yu, Jacob Relles, Sheldon X.-D. Tan:
  A structured parallel periodic Arnoldi shooting algorithm for RF-PSS analysis based on GPU platforms. 13-18
  
• Hui Xu, Guoyong Shi, Xiaopeng Li:
  Hierarchical exact symbolic analysis of large analog integrated circuits by symbolic stamps. 19-24
  
• Miao Hu, Hai Li, Yiran Chen, Xiaobin Wang, Robinson E. Pino:
  Geometry variations analysis of TiO2 thin-film and spintronic memristors. 25-30
  
• Xiangyu Dong, Yuan Xie:
  AdaMS: Adaptive MLC/SLC phase-change memory design for file storage. 31-36
  
• Joonsoo Kim, Joonsoo Lee, Jacob A. Abraham:
  System accuracy estimation of SRAM-based device authentication. 37-42
  
• Wulong Liu, Yu Wang, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang:
  On-chip hybrid power supply system for wireless sensor nodes. 43-48
  
• Zheng Zhang, Qing Wang, Ngai Wong, Luca Daniel:
  A moment-matching scheme for the passivity-preserving model order reduction of indefinite descriptor systems with possible polynomial parts. 49-54
  
• Xiang Wang, Qing Wang, Zheng Zhang, Quan Chen, Ngai Wong:
  Balanced truncation for time-delay systems via approximate Gramians. 55-60
  
• Yu Bi, Pieter Harpe, N. P. van der Meijs:
  Efficient sensitivity-based capacitance modeling for systematic and random geometric variations. 61-66
  
• Wenjian Yu, Chao Hu, Wangyang Zhang:
  Parallel statistical capacitance extraction of on-chip interconnects with an improved geometric variation model. 67-72
  
• Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng:
  A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. 73-74
  
• Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
  A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. 75-76
  
• Dan Bao, Chuan Wu, Yan Ying, Yun Chen, Xiaoyang Zeng:
  A 4.32 mm² 170mW LDPC decoder in 0.13μm CMOS for WiMax/Wi-Fi applications. 77-78
  
• Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
  All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. 79-80
  
• Takehiko Amaki, Masanori Hashimoto, Takao Onoye:
  Jitter amplifier for oscillator-based true random number generator. 81-82
  
• Jun Furuta, Chikara Hamanaka, Kazutoshi Kobayashi, Hidetoshi Onodera:
  A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. 83-84
  
• Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo:
  Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism. 85-86
  
• Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo:
  Geyser-2: The second prototype CPU with fine-grained run-time power gating. 87-88
  
• Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
  An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. 89-90
  
• Shuming Chen, Xiaowen Chen, Yi Xu, Jianghua Wan, Jianzhuang Lu, Xiangyuan Liu, Shenggang Chen:
  Design and chip implementation of a heterogeneous multi-core DSP. 91-92
  
• Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo:
  A low-power management technique for high-performance domino circuits. 93-94
  
• Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo:
  Design and evaluation of variable stages pipeline processor chip. 95-96
  
• Shuo-Hung Chen, Hsiao-Mei Lin, Ching-Chou Hsieh, Chih-Tsun Huang, Jing-Jia Liou, Yeh-Ching Chung:
  TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler. 97-98
  
• Yu-Han Yuan, Wei-Ming Chen, Hsi-Pin Ma:
  Design and implementation of a high performance closed-loop MIMO communications with ultra low complexity handset. 99-100
  
• Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa:
  A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection technique. 101-102
  
• Wei Deng, Kenichi Okada, Akira Matsuzawa:
  An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation. 103-104
  
• Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Wei-Chih Lai, Yarsun Hsu:
  A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. 105-106
  
• Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada:
  A fully integrated shock wave transmitter with an on-chip dipole antenna for pulse beam-formability in 0.18-μm CMOS. 107-108
  
• Xin Zhang, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai:
  An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS. 109-110
  
• Wen Fan, Oliver Chiu-sing Choy:
  Robust and efficient baseband receiver design for MB-OFDM UWB system. 111-112
  
• Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
  A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder. 113-114
  
• Ting Gao, Wei Li, Ning Li, Junyan Ren:
  A 80-400 MHz 74 dB-DR Gm-C low-pass filter with a unique auto-tuning system. 115-116
  
• Chenchang Zhan, Wing-Hung Ki:
  An adaptively biased low-dropout regulator with transient enhancement. 117-118
  
• Dong Qiu, Ting Yi, Zhiliang Hong:
  A low-power triple-mode sigma-delta DAC for reconfigurable (WCDMA/TD-SCDMA/GSM) transmitters. 119-120
  
• Mohiuddin Hafiz, Nobuo Sasaki, Kentaro Kimoto, Takamaro Kikkawa:
  A simple non-coherent solution to the UWB-IR communication. 121-122
  
• Pratyush Kumar, Lothar Thiele:
  Thermally optimal stop-go scheduling of task graphs with real-time constraints. 123-128
  
• Yazhi Huang, Tiantian Liu, Chun Jason Xue:
  Register allocation for write activity minimization on non-volatile main memory. 129-134
  
• Vivek Chaturvedi, Gang Quan:
  Leakage conscious DVS scheduling for peak temperature minimization. 135-140
  
• Hessam Kooti, Deepak Mishra, Eli Bozorgzadeh:
  Reconfiguration-aware real-time scheduling under QoS constraint. 141-146
  
• Bin Li, Zhen Fang, Ravi Iyer:
  Template-based memory access engine for accelerators in SoCs. 147-153
  
• Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch:
  Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems. 154-159
  
• Wan-Ting Su, Jih-Sheng Shen, Pao-Ann Hsiung:
  Network-on-Chip router design with Buffer-Stealing. 160-164
  
• Tae-ho Shin, Hyunok Oh, Soonhoi Ha:
  Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph. 165-170
  
• Mysore Sriram:
  A fast approximation technique for power grid analysis. 171-175
  
• Khaled Salah, Hani Ragai, Yehea I. Ismail, Alaa El Rouby:
  Equivalent lumped element models for various n-port Through Silicon Vias networks. 176-183
  
• Xuchu Hu, Matthew R. Guthaus:
  Clock tree optimization for Electromagnetic Compatibility (EMC). 184-189
  
• Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin:
  Pulser gating: A clock gating of pulsed-latch circuits. 190-195
  
• Meng-Fan Chang, Pi-Feng Chiu, Shyh-Shyuan Sheu:
  Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC. 197-203
  
• Yiran Chen, Hai Li:
  Emerging sensing techniques for emerging memories. 204-210
  
• Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie:
  A frequent-value based PRAM memory architecture. 211-216
  
• Wei Lu, Kuk-Hwan Kim, Ting Chang, Siddharth Gaba:
  Two-terminal resistive switches (memristors) for memory and logic applications. 217-223
  
• Dip Goswami, Reinhard Schneider, Samarjit Chakraborty:
  Co-design of cyber-physical systems via controllers with flexible delay constraints. 225-230
  
• Ang-Chih Hsieh, Chun-Cheng Liu, TingTing Hwang:
  Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation. 231-236
  
• Deepak Gangadharan, Samarjit Chakraborty, Roger Zimmermann:
  Fast hybrid simulation for accurate decoded video quality assessment on MPSoC platforms with resource constraints. 237-242
  
• Marisha Rawlins, Ann Gordon-Ross:
  On the interplay of loop caching, code compression, and cache configuration. 243-248
  
• Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham:
  Path criticality computation in parameterized statistical timing analysis. 249-254
  
• Pratyush Kumar, David Atienza:
  Run-time adaptable on-chip thermal triggers. 255-260
  
• Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong:
  Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. 261-266
  
• Jun Zhou, Senthil Jayapal, Jan Stuyt, Jos Huisken, Harmke de Groot:
  The impact of inverse narrow width effect on sub-threshold device sizing. 267-272
  
• Ming Gao, Peter Lisherness, Kwang-Ting (Tim) Cheng:
  Post-silicon bug detection for variation induced electrical bugs. 273-278
  
• Jing-Jia Liou, Ying-Yen Chen, Chun-Chia Chen, Chung-Yen Chien, Kuo-Li Wu:
  Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs. 279-284
  
• Masanori Hashimoto:
  Run-time adaptive performance compensation using on-chip sensors. 285-290
  
• David Brooks:
  The alarms project: A hardware/software approach to addressing parameter variations. 291
  
• Miroslav N. Velev, Ping Gao:
  Automatic formal verification of reconfigurable DSPs. 293-296
  
• Chung-Yang Huang, Yu-Fan Yin, Chih-Jen Hsu, Thomas B. Huang, Ting-Mao Chang:
  SoC HW/SW verification and validation. 297-300
  
• Masahiro Fujita:
  Utilizing high level design information to speed up post-silicon debugging. 301-305
  
• Andreas G. Veneris, Brian Keng, Sean Safarpour:
  From RTL to silicon: The case for automated debug. 306-310
  
• Rainer Dömer, Weiwei Chen, Xu Han, Andreas Gerstlauer:
  Multi-core parallel simulation of System-level Description Languages. 311-316
  
• Masoud Zamani, Mehdi Baradaran Tahoori:
  Variation-aware logic mapping for crossbar nano-architectures. 317-322
  
• Tan Yan, Qiang Ma, Scott Chilstedt, Martin D. F. Wong, Deming Chen:
  Routing with graphene nanoribbons. 323-329
  
• Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, Chien-Nan Jimmy Liu:
  ILP-based inter-die routing for 3D ICs. 330-335
  
• Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot, David Z. Pan, Giovanni De Micheli:
  CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits. 336-343
  
• Sudeep Pasricha, Shirish Bahirat:
  OPAL: A multi-layer hybrid photonic NoC for 3D ICs. 345-350
  
• Jin Ouyang, Yuan Xie:
  Enabling quality-of-service in nanophotonic network-on-chip. 351-356
  
• Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li:
  Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip. 357-362
  
• Wenmin Hu, Zhonghai Lu, Axel Jantsch, Hengzhu Liu:
  Power-efficient tree-based multicast support for Networks-on-Chip. 363-368
  
• Jason Helge Anderson, Qiang Wang:
  Area-efficient FPGA logic elements: Architecture and synthesis. 369-375
  
• Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin:
  Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. 376-381
  
• Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu, Chung-Yang Huang:
  A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization. 382-387
  
• Chi-Chen Peng, Chen Dong, Deming Chen:
  SETmap: A soft error tolerant mapping algorithm for FPGA designs with low power. 388-393
  
• Soichi Inoue, Sachiko Kobayashi:
  All-out fight against yield losses by design-manufacturing collaboration in nano-lithography era. 395-401
  
• Sam Sivakumar:
  EUV lithography: Prospects and challenges. 402
  
• Jack J. H. Chen, Faruk Krecinic, Jen-Hom Chen, Raymond P. S. Chen, Burn J. Lin:
  Future electron-beam lithography and implications on design and CAD tools. 403-404
  
• Chul-Hong Park, David Z. Pan, Kevin Lucas:
  Exploration of VLSI CAD researches for early design rule evaluation. 405-406
  
• Marius Gligor, Frédéric Pétrot:
  Handling dynamic frequency changes in statically scheduled cycle-accurate simulation. 407-412
  
• Ryo Kawahara, Kenta Nakamura, Kouichi Ono, Takeo Nakada, Yoshifumi Sakamoto:
  Coarse-grained simulation method for performance evaluation a of shared memory system. 413-418
  
• Wei Zang, Ann Gordon-Ross:
  T-SPaCS - A two-level single-pass cache simulation methodology. 419-424
  
• Hector Posadas, Luis Diaz, Eugenio Villar:
  Fast data-cache modeling for native co-simulation. 425-430
  
• Yung-Chang Chang, Ching-Te Chiu, Shih-Yin Lin, Chung-Kai Liu:
  On the design and analysis of fault tolerant NoC architecture using spare routers. 431-436
  
• Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li:
  A resilient on-chip router design through data path salvaging. 437-442
  
• Sudeep Pasricha, Yong Zou:
  NS-FTR: A fault tolerant routing scheme for networks on chip with permanent and runtime intermittent faults. 443-448
  
• Zhiliang Qian, Chi-Ying Tsui:
  A thermal-aware application specific routing algorithm for Network-on-Chip design. 449-454
  
• Yu Pang, Katarzyna Radecka, Zeljko Zilic:
  An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits. 455-460
  
• Rami Beidas, Wai Sum Mong, Jianwen Zhu:
  Register pressure aware scheduling for high level synthesis. 461-466
  
• James Williamson, Yinghai Lu, Li Shang, Hai Zhou, Xuan Zeng:
  Parallel cross-layer optimization of high-level synthesis and physical design. 467-472
  
• Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto:
  Network flow-based simultaneous retiming and slack budgeting for low power design. 473-478
  
• Brian Keng, Andreas G. Veneris:
  Managing complexity in design debugging with sequential abstraction and refinement. 479-484
  
• Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo:
  Facilitating unreachable code diagnosis and debugging. 485-490
  
• Hongxia Fang, Zhiyuan Wang, Xinli Gu, Krishnendu Chakrabarty:
  Deterministic test for the reproduction and detection of board-level functional failures. 491-496
  
• Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
  Equivalence checking of scheduling with speculative code transformations in high-level synthesis. 497-502
  
• Kyoung-Hwan Lim, Taewhan Kim:
  An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. 503-508
  
• Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu:
  On applying erroneous clock gating conditions to further cut down power. 509-514
  
• Li Li, Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng:
  Low power discrete voltage assignment under clock skew scheduling. 515-520
  
• Yanling Zhi, Hai Zhou, Xuan Zeng:
  A practical method for multi-domain clock skew optimization. 521-526
  
• Jia-Ru Chuang, Jai-Ming Lin:
  Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction. 527-532
  
• Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak:
  Cut-demand based routing resource allocation and consolidation for routability enhancement. 533-538
  
• Wen-Hao Liu, Yih-Lang Li:
  Negotiation-based layer assignment for via count and via overflow minimization. 539-544
  
• Michael D. Moffitt, Chin Ngai Sze:
  Wire synthesizable global routing for timing closure. 545-550
  
• Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Hirofumi Iwato:
  Biological information sensing technologies for medical, health care, and wellness applications. 551-555
  
• Srinivasa R. Sridhara:
  Ultra-low power microcontrollers for portable, wearable, and implantable medical electronics. 556-560
  
• Valer Pop, Ruben de Francisco, Hans Pflug, Juan Santana, Hubregt J. Visser, Ruud J. M. Vullers, Harmke de Groot, Bert Gyselinckx:
  Human++: Wireless autonomous sensor technology for body area networks. 561-566
  
• Koji Ara, Tomoaki Akitomi, Nobuo Sato, Satomi Tsuji, Miki Hayakawa, Yoshihiro Wakisaka, Norio Ohkubo, Rieko Otsuka, Fumiko Beniyama, Norihiko Moriwaki, Kazuo Yano:
  Healthcare of an organization: Using wearable sensors and feedback system for energizing workers. 567-572
  
• Junwhan Ahn, Imyong Lee, Kiyoung Choi:
  A polynomial-time custom instruction identification algorithm based on dynamic programming. 573-578
  
• Jiawei Huang, John Lach:
  Exploring the fidelity-efficiency design space using imprecise arithmetic. 579-584
  
• Juinn-Dar Huang, Yi-Hang Chen, Ya-Chien Ho:
  Throughput optimization for latency-insensitive system with minimal queue insertion. 585-590
  
• Yi-Siou Chen, Lih-Yih Chiou, Hsun-Hsiang Chang:
  A fast and effective dynamic trace-based method for analyzing architectural performance. 591-596
  
• Ashutosh Chakraborty, David Z. Pan:
  Controlling NBTI degradation during static burn-in testing. 597-602
  
• Yongho Lee, Taewhan Kim:
  A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs. 603-608
  
• Ming-Chao Lee, Yu-Guang Chen, Ding-Kei Huang, Shih-Chieh Chang:
  NBTI-aware power gating design. 609-614
  
• Tung-Yeh Wu, Shih-Hsin Hu, Jacob A. Abraham:
  Robust power gating reactivation by dynamic wakeup sequence throttling. 615-620
  
• Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, David Z. Pan:
  Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. 621-626
  
• X. Gao, L. Macchiarlo:
  Track routing optimizing timing and yield. 627-632
  
• Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao:
  Simultaneous redundant via insertion and line end extension for yield optimization. 633-638
  
• Kang Zhao, Jinian Bian:
  Pruning-based trace signal selection algorithm. 639-644
  
• Tatsuo Nakajima, Yuki Kinebuchi, Hiromasa Shimada, Alexandre Courbot, Tsung-Han Lin:
  Temporal and spatial isolation in a virtualization layer for multi-core processor based information appliances. 645-652
  
• Jason Loew, Jesse Elwell, Dmitry Ponomarev, Patrick H. Madden:
  Mathematical limits of parallel computation for embedded systems. 653-660
  
• Jen-Wei Hsieh, Yuan-Hao Chang, Wei-Li Lee:
  An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs. 661-667
  
• Tiefei Zhang, Ying-Jheng Chen, Che-Wei Chang, Chuan-Yue Yang, Tei-Wei Kuo, Tianzhou Chen:
  Power management strategies in data transmission. 668-675
  
• Mingzhi Gao, Zuochang Ye, Dajie Zeng, Yan Wang, Zhiping Yu:
  Robust spatial correlation extraction with limited sample via L1-norm penalty. 677-682
  
• Kenichi Shinkai, Masanori Hashimoto:
  Device-parameter estimation with on-chip variation sensors considering random variability. 683-688
  
• Jianxin Fang, Sachin S. Sapatnekar:
  Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability. 689-694
  
• Chih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaushik Roy:
  Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays. 695-700
  
• Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang:
  A physical-location-aware fault redistribution for maximum IR-drop reduction. 701-706
  
• Vikas Chandra, Robert C. Aitken:
  On the impact of gate oxide degradation on SRAM dynamic and static write-ability. 707-712
  
• Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu:
  A self-testing and calibration method for embedded successive approximation register ADC. 713-718
  
• Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita:
  On-chip dynamic signal sequence slicing for efficient post-silicon debugging. 719-724
  
• Abhishek A. Sinkar, Nam Sung Kim:
  AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors. 725-730
  
• Junhe Gan, Flavius Gruian, Paul Pop, Jan Madsen:
  Energy/reliability trade-offs in fault-tolerant event-triggered distributed embedded systems. 731-736
  
• Jingqing Mu, Roman L. Lysecky:
  Profile assisted online system-level performance and power estimation for dynamic reconfigurable embedded systems. 737-742
  
• Jiayin Li, Meikang Qiu, Jianwei Niu, Tianzhou Chen:
  Battery-aware task scheduling in distributed mobile systems with lifetime constraint. 743-748
  
• Takao Suzuki:
  Advanced system LSIs for home 3D system. 749-754
  
• Yoshiyuki Kitasho, Yu Kikuchi, Takayoshi Shimazawa, Yasuo Ohara, Masafumi Takahashi, Yoshio Masubuchi, Yukihito Oowaki:
  Development of low power and high performance application processor (T6G) for multimedia mobile applications. 755-759
  
• Atsuki Inoue:
  Design constraint of fine grain supply voltage control LSI. 760-765
  
• Masaru Takahashi:
  FPGA prototyping using behavioral synthesis for improving video processing algorithm and FHD TV SoC design. 766-769
  
• Nobuyuki Nishiguchi:
  An RTL-to-GDS2 design methodology for advanced system LSI. 770-774
  
• Duo Ding, Andres J. Torres, Fedor G. Pikus, David Z. Pan:
  High performance lithographic hotspot detection using hierarchically refined machine learning. 775-780
  
• Jen-Yi Wuu, Fedor G. Pikus, Andres J. Torres, Malgorzata Marek-Sadowska:
  Rapid layout pattern classification. 781-786
  
• Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao:
  Mask cost reduction with circuit performance consideration for self-aligned double patterning. 787-792
  
• Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng:
  Post-routing layer assignment for double patterning. 793-798
  
• Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
  Fault simulation and test generation for clock delay faults. 799-805
  
• Jia Li, Qiang Xu, Dong Xiang:
  Compression-aware capture power reduction for at-speed testing. 806-811
  
• J. M. Howard, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker:
  Fault diagnosis aware ATE assisted test response compaction. 812-817
  
• Hideo Fujiwara, Katsuya Fujiwara, Hideo Tamamoto:
  Secure scan design using shift register equivalents against differential behavior attack. 818-823
  
• Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho:
  An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs. 825-830
  
• Alireza Rakhshanfar, Jason Helge Anderson:
  An integer programming placement approach to FPGA clock power reduction. 831-836
  
• Ren-Jie Lee, Hung-Ming Chen:
  Row-based area-array I/O design planning in concurrent chip-package design flow. 837-842
  
• Qiang Ma, Hui Kong, Martin D. F. Wong, Evangeline F. Y. Young:
  A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing. 843-848
  

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