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ORCID10th Asian Test Symposium 2001: Kyoto, Japan
- 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan. IEEE Computer Society 2001, ISBN 0-7695-1378-6
Keynote Address
- Janusz Rajski:
DFT for High-Quality Low Cost Manufacturing Test. 3-
Design for Testability
- Md. Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara:
Design for Hierarchical Two-Pattern Testability of Data Paths. 11-16 - Dong Xiang, Yi Xu:
A Multiple Phase Partial Scan Design Method. 17-22 - Hiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume, Takeomi Tamesada:
Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States. 23-
Fault Modeling for Memories
- Matthias Klaus, Ad J. van de Goor:
Tests for Resistive and Capacitive Defects in Address Decoders. 31-36 - Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers:
Detecting Unique Faults in Multi-port SRAMs. 37-42 - Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter:
A Memory Specific Notation for Fault Modeling. 43-
Diagnosis
- Irith Pomeranz:
On Pass/Fail Dictionaries for Scan Circuits . 51-56 - Michael Gössel, Vitalij Ocheretnij, S. Chakrabarty:
Diagnosis by Repeated Application of Specific Test Inputs and by Output Monitoring of the MISA. 57-62 - Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu:
Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. 63-
ATPG
- Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu:
Test Generation for Double Stuck-at Faults. 71-75 - Tsuyoshi Shinogi, Tomokazu Kanbayashi, Tomohiro Yoshikawa, Shinji Tsuruoka, Terumine Hayashi:
Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems. 76-81 - Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits. 82-
Embedded Memory Test
- Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu:
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. 91-96 - Davide Appello
, Fulvio Corno, M. Giovinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis. 97-102 - Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang:
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. 103-
IDDQ and Diagnosis Test
- Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita:
IDDQ Sensing Technique for High Speed IDDQ Testing. 111-116 - Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application. 117-122 - Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Yasuo Sato:
An Approach to Improve the Resolution of Defect-Based Diagnosis. 123-
Test Compaction
- Irith Pomeranz, Sudhakar M. Reddy:
A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits. 131-136 - Kwame Osei Boateng, Hideaki Konishi, Tsuneo Nakata:
A Method of Static Compaction of Test Stimuli. 137-144 - Hideyuki Ichihara, Atsuhiro Ogawa, Tomoo Inoue, Akio Tamura:
Dynamic Test Compression Using Statistical Coding. 143-
Pattern Generation for Memory Test
- Mill-Jer Wang, R.-L. Jiang, J.-W. Hsia, Chih-Hu Wang, Jwu E. Chen:
Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing. 151-156 - Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
Memory Read Faults: Taxonomy and Automatic Test Generation. 157-163 - Serge N. Demidenko, Ad J. van de Goor, S. Henderson, P. Knoppers:
Simulation and Development of Short Transparent Tests for RAM. 164-
Virtual Tester and Beam Testing
- Junichi Hirase:
Test Time Reduction through Minimum Execution of Tester-Hardware Setting Instructions. 173-178 - Norio Kuji, Takako Ishihara:
EB-Testing-Pad Method and Its Evaluation by Actual Devices. 179-184 - Jeffrey A. Block, William K. Lo, Chris Shaw:
Benefits of Phase Interference Detection to IC Waveform Probing. 185-
SoC Test Access Mechanism
- Tomokazu Yoneda, Hideo Fujiwara:
A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability. 193-198 - Ozgur Sinanoglu, Alex Orailoglu:
Compaction Schemes with Minimum Test Application Time. 199-204 - Zahra Sadat Ebadi, André Ivanov:
Design of an Optimal Test Access Architecture Using a Genetic Algorithm. 205-
RTL ATPG
- Huawei Li, Yinghua Min, Zhongcheng Li:
An RT-Level ATPG Based on Clustering of Circuit States. 213-218 - Zhigang Yin, Yinghua Min, Xiaowei Li:
An Approach to RTL Fault Extraction and Test Generation. 219-224 - Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero:
Effective Techniques for High-Level ATPG. 225-
Delay Test
- Yun Shao, Sudhakar M. Reddy, Seiji Kajihara, Irith Pomeranz:
An Efficient Method to Identify Untestable Path Delay Faults. 233-238 - Kee Sup Kim, Rathish Jayabharathi, Craig Carstens:
SpeedGrade: An RTL Path Delay Fault Simulator. 239-243 - Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo:
Test Generation for Multiple-Threshold Gate-Delay Fault Model. 244-
SoC Test Scheduling
- Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. 253-258 - Erik Larsson, Zebo Peng:
Test Scheduling and Scan-Chain Division under Power Constraint. 259-264 - Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy:
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. 265-
FSM Test
- Parag K. Lala, Alvernon Walker:
A Unified Scheme for Designing Testable State Machines. 273-278 - Samrat Goswami, Anupam Chanda, D. Roy Choudhury:
Generation of an Ordered Sequence of Test Vectors for Single State Transition Faults in Large Sequential Machines. 279-284 - Biplab K. Sikdar, Samir Roy, Debesh K. Das:
Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis. 285-
Online Testing and Fault Injection line
- Emmanuel Simeu, Ahmad Abdelhay, Mohammad A. Naal:
Robust Self Concurrent Test of Linear Digital Systems. 293-298 - Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Luca Tagliaferri:
Control-Flow Checking via Regular Expressions. 299-303 - Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
FPGA-Based Fault Injection for Microprocessor Systems. 304-
Advances in BIST
- Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara:
BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths. 313-318 - Sobeeh Almukhaizim, Peter Petrov, Alex Orailoglu:
Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit. 319-324 - Bernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater:
A SmartBIST Variant with Guaranteed Encoding. 325-
Analog Test
- Yoshikazu Takahashi:
MEMS Comb-Actuator Resonance Measurement Method Using the 2nd Harmonics of the GND Current. 333-337 - Zhen Guo, Xi Min Zhang, Jacob Savir, Yun-Qing Shi:
On Test and Characterization of Analog Linear Time-Invariant Circuits Using Neural Networks. 338-343 - Achintya Halder, Abhijit Chatterjee:
Specification Based Digital Compatible Built-in Test of Embedded Analog Circuits. 344-
Fault Tolerance
- Junichi Hirase:
Yield Increase of VLSI after Redundancy-Repairing. 353-358 - Naotake Kamiura, Yasuyuki Taniguchi, Teijiro Isokawa, Nobuyuki Matsui:
An Improvement in Weight-Fault Tolerance of Feedforward Neural Networks. 359-364 - Vitalij Ocheretnij, Egor S. Sogomonyan, Michael Gössel:
A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes. 365-
Various Ideas for BIST
- Ismet Bayraktaroglu, Alex Orailoglu:
Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck? 373-378 - Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara:
Hybrid BIST Using Partially Rotational Scan. 379-384 - Biplab K. Sikdar, Niloy Ganguly, Aniket Karmakar, Subha Sankar Chowdhury, Parimal Pal Chaudhuri:
Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI Circuits. 385-390 - Dongkyu Youn, Taehyung Kim, Sungju Park:
A Microcode-Based Memory BIST Implementing Modified March Algorithm. 391-395 - Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi:
Fault Simulation for VHDL Based Test Bench and BIST Evaluation. 396-
Analog/Mixed Signal Test
- Biranchinath Sahu, Abhijit Chatterjee:
Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models. 405-410 - Alfred V. Gomes, Abhijit Chatterjee:
Distance Constrained Dimensionality Reduction for Parametric Fault Test Generator. 411-416 - Andreas Lechner, Andrew Richardson, B. Hermes:
Short Circuit Faults in State-of-the-Art ADCs - Are They Hard or Soft? 417-422 - Jeng-Horng Tsai, Ming-Jun Hsiao, Tsin-Yuan Chang:
An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters. 423-
Verification
- Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model. 431-436 - Bin Zhou, Tomohiro Yoneda, Chris J. Myers:
Framework of Timed Trace Theoretic Verification Revisited. 437-442 - Ilia Polian, Wolfgang Günther, Bernd Becker:
Efficient Pattern-Based Verification of Connections to IP Cores . 443-448 - Bipul Chandra Paul, Seung Hoon Choi, Yonghee Im, Kaushik Roy:
Design Verification and Robust Design Technique for Cross-Talk Faults. 449-
DFT Application to Real Chips
- Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Toyohito Ikeya, Masatoshi Kawashima:
A Practical Logic BIST for ASIC Designs. 457 - Tetsuo Kamada:
Tx7901 Dft. 458 - Toshinobu Ono, Akira Kozawa, Takashi Kimura, Yoshihiro Konno, Koji Saga:
An Application of Partial Scan Techniques to a High-End System LSI Design. 459 - Hisayoshi Hanai, Shinji Yamada, Hisaya Mori, Eisaku Yamashita, Teruhiko Funakura:
Built-out Self-Test (BOST) for Analog Circuits in a System LSI: Test Solution to Reduce Test Costs. 460 - Masato Suzuki, R. Shimizu, N. Naka, K. Nakamura:
High-Speed Interface Testing. 461 - Tetsuji Kishi, Mitsuyasu Ohta, Takashi Taniguchi, Hiroshi Kadota:
A New Inter-Core Built-In-Self-Test Circuits for Tri-State Buffers in the System on a Chip. 462 - Xiaoqing Wen, Hsin-Po Wang:
A Flexible Logic BIST Scheme and Its Application to SoC Designs. 463
Practical Ideas from Universities
- Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin:
Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. 467 - Shiyi Xu:
Non-exhaustive Parity Testing. 468 - Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita:
Built-in Self-Test for State Faults Induced by Crosstalk in Sequential Circuits. 469 - Tsung-Chu Huang, Kuen-Jong Lee:
A Low-Power LFSR Architecture. 470
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