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ORCID23rd Asian Test Symposium 2014: Hangzhou, China
- 23rd IEEE Asian Test Symposium, ATS 2014, Hangzhou, China, November 16-19, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-6030-9
Session 1A: 3D Testing
- Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
:
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. 1-6 - Kele Shen, Dong Xiang, Zhou Jiang:
Dual-Speed TAM Optimization of 3D SoCs for Mid-bond and Post-bond Testing. 7-12 - Katherine Shu-Min Li, Sying-Jyan Wang, Jia-Lin Wu, Cheng-You Ho, Yingchieh Ho, Ruei-Ting Gu, Bo-Chuan Cheng:
Optimized Pre-bond Test Methodology for Silicon Interposer Testing. 13-18
Session 1B: Reliability
- Huaguo Liang, Zhi Wang, Zhengfeng Huang, Aibin Yan:
Design of a Radiation Hardened Latch for Low-Power Circuits. 19-24 - Da Cheng, Fangzhou Wang, Feng Gao, Sandeep K. Gupta:
Optimal Redundancy Designs for CNFET-Based Circuits. 25-32 - Jiajia Jiao, Yuzhuo Fu:
A Heuristically Mechanical Model for Accurate and Fast Soft Error Analysis. 33-38
Special Session 1C: Resilient Circuit Design and Test
- Suvadeep Banerjee, Álvaro Gómez-Pau, Abhijit Chatterjee, Jacob A. Abraham:
Error Resilient Real-Time State Variable Systems for Signal Processing and Control. 39-44 - Yukio Mitsuyama, Hidetoshi Onodera:
Variability and Soft-Error Resilience in Dependable VLSI Platform. 45-50 - Farshad Firouzi, Fangming Ye, Saman Kiamehr, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori:
Adaptive Mitigation of Parameter Variations. 51-56
Session 2A: Testing of Emerging Technologies
- Zipeng Li, Trung Anh Dinh, Tsung-Yi Ho, Krishnendu Chakrabarty:
Reliability-Driven Pipelined Scan-Like Testing of Digital Microfluidic Biochips. 57-62 - Shao-Feng Hung, Long-Yi Lin, Hao-Chiao Hong:
A Cost-Effective Stimulus Generator for Battery Channel Characterization in Electric Vehicles. 63-67 - Bappaditya Mondal, Dipak Kumar Kole, Debesh Kumar Das, Hafizur Rahaman:
Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference Method. 68-73
Session 2B: SoC Testing
- Maciej Trawka, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jakub Janicki, Jerzy Tyszer:
High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs. 74-80 - Taewoo Han, Inhyuk Choi, Hyunggoy Oh, Sungho Kang:
A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System. 81-86 - Atefe Dalirsani, Nadereh Hatami, Michael E. Imhof, Marcus Eggenberger, Gert Schley, Martin Radetzki, Hans-Joachim Wunderlich:
On Covering Structural Defects in NoCs by Functional Tests. 87-92 - Farrokh Ghani Zadegan, Erik Larsson, Artur Jutman, Sergei Devadze, Rene Krenz-Baath:
Design, Verification, and Application of IEEE 1687. 93-100
Session 3A: Post-silicon Validation
- Fan Yang, Sreejit Chakravarty, Arun Gunda, Nicole Wu, Jianyu Ning:
Silicon Evaluation of Cell-Aware ATPG Tests and Small Delay Tests. 101-106 - Xiaobing Shi, Nicola Nicolici:
On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli. 107-112 - Cheng Xue, R. D. (Shawn) Blanton:
Predicting IC Defect Level Using Diagnosis. 113-118
Session 3B: Testability and Test Generation
- Kun-Han Tsai:
Testability-Driven Fault Sampling for Deterministic Test Coverage Estimation of Large Designs. 119-124 - Chandan Kumar, Fadi Maamari, Kiran Vittal, Wilson Pradeep, Rajesh Tiwari, Srivaths Ravi:
Methodology for Early RTL Testability and Coverage Analysis and Its Application to Industrial Designs. 125-130 - Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker:
Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects. 131-136
Session 4A: Yield Optimization of Memory
- Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume, Seiji Kajihara:
Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories. 137-142 - Kuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo:
Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs. 143-148 - Jizhe Zhang, Sandeep Gupta:
SRAM Array Yield Estimation under Spatially-Correlated Process Variation. 149-155
Session 4B: On-Line Parameter Testing
- Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura:
Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test. 156-161 - Shi-Yu Huang, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng:
On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs. 162-167 - Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada:
A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge. 168-173
Session 5A: Power/Temperature-Aware Testing
- Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low Power Test Compression with Programmable Broadcast-Based Control. 174-179 - Li Ling, Jianhui Jiang:
Exploit Dynamic Voltage and Frequency Scaling for SoC Test Scheduling under Thermal Constraints. 180-185 - Vasileios Tenentes, S. Saqib Khursheed, Bashir M. Al-Hashimi, Shida Zhong, Sheng Yang:
High Quality Testing of Grid Style Power Gating. 186-191
Session 5B: Trojan/Fault Detection with High Resolution
- Byeongju Cha, Sandeep K. Gupta:
A Resizing Method to Minimize Effects of Hardware Trojans. 192-199 - Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee:
High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure. 200-205 - John A. Porche, R. D. (Shawn) Blanton:
Physically-Aware Diagnostic Resolution. 206-211
Session 6A: Analog/Memory Testing
- Guillaume Renaud, Manuel J. Barragán, Salvador Mir, Marc Sabut:
On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test. 212-217 - Jose Moreira, Hubert Werkmann, Masahiro Ishida, Bernhard Roth, Volker Filsinger, Sui-Xia Yang:
An ATE Based 32 Gbaud PAM-4 At-Speed Characterization and Testing Solution. 218-223 - Yong-Xiao Chen, Jin-Fu Li:
Testing of Non-volatile Logic-Based System Chips. 224-229 - Kelson Gent, Michael S. Hsiao:
Dual-Purpose Mixed-Level Test Generation Using Swarm Intelligence. 230-235
Panel Session 6B: Big Data for Test
- Fan Lin, Chun-Kai Hsu, Kwang-Ting Cheng:
Learning from Production Test Data: Correlation Exploration and Feature Engineering. 236-241 - Harry H. Chen:
Perspectives on Test Data Mining from Industrial Experience. 242-247
Special Session 6C: In-Field Techniques for Performance Adaption, Test, and Power-Noise Diagnosis
- Masanori Hashimoto:
Opportunities and Verification Challenges of Run-Time Performance Adaptation. 248-253 - Seiji Kajihara, Yousuke Miyake, Yasuo Sato, Yukiya Miura:
An On-Chip Digital Environment Monitor for Field Test. 254-257 - Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura:
On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips. 258-262
Session 7A: Timing Variation Detection
- Yun Cheng, Huawei Li, Xiaowei Li:
An On-Line Timing Error Detection Method for Silicon Debug. 263-268 - Mehdi Sadi, Zoe Conroy, Bill Eklow, Matthias Kamm, Nematollah Bidokhti, Mark Mohammad Tehranipoor:
An All Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SoCs. 269-274 - Jibing Qiu, Guihai Yan, Xiaowei Li:
On-Chip Delay Sensor for Environments with Large Temperature Fluctuations. 275-280
Session 7B: Delay Testing
- Jie Zou, Chao Han, Adit D. Singh:
Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing. 281-286 - Chung-Yun Wang, Yu-Yi Chen, Jiun-Lang Huang, Xuan-Lun Huang:
FPGA-Based Subset Sum Delay Lines. 287-291 - Yussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue:
Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units. 292-297
Special Session 7C: High Quality System Level Test and Diagnosis
- Artur Jutman, Matteo Sonza Reorda, Hans-Joachim Wunderlich:
High Quality System Level Test and Diagnosis. 298-305
Session 8A: Diagnosis
- Cheng-Hung Wu, Kuen-Jong Lee:
An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults. 306-311 - Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Etienne Auvray:
On the Generation of Diagnostic Test Set for Intra-cell Defects. 312-317 - Huaxing Tang, Brady Benware, Michael Reese, Joseph Caroselli, Thomas Herrmann, Friedrich Hapke, Robert Tao, Wu-Tung Cheng, Manish Sharma:
Diagnosing Cell Internal Defects Using Analog Simulation-Based Fault Models. 318-323
Session 8B: Test Compression
- Sying-Jyan Wang, Che-Wei Kao, Katherine Shu-Min Li:
Improving Output Compaction Efficiency with High Observability Scan Chains. 324-329 - Emil Gizdarski:
Two-Step Dynamic Encoding for Linear Decompressors. 330-335 - Anshuman Chandra, Subramanian Chebiyam, Rohit Kapur:
A Case Study on Implementing Compressed DFT Architecture. 336-341
Special Session 8C: Hardware Security
- Yu Bi, Pierre-Emmanuel Gaillardon, Xiaobo Sharon Hu, Michael T. Niemier, Jiann-Shiun Yuan, Yier Jin:
Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs. 342-347 - Alison Hosey, Md. Tauhidur Rahman, Kan Xiao, Domenic Forte, Mohammad Tehranipoor:
Advanced Analysis of Cell Stability for Reliable SRAM PUFs. 348-353 - Junfeng Fan, Hua Xie, Yiwei Zhang:
On the Use of Scan Chain to Improve Physical Attacks (Extended Abstract). 354-357
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