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ORCIDCDES 2005: Las Vegas, Nevada, USA
- Laurence Tianruo Yang, Hamid R. Arabnia, Yiming Li, Salam N. Salloum, José G. Delgado-Frias:
Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005. CSREA Press 2005, ISBN 1-932415-54-8
Failure Prevention in Computer Systems
- Keith Whisnant, Kenny C. Gross, Natasha Lingurovska:
Proactive Fault Monitoring in Enterprise Servers. CDES 2005: 3-10 - Anton Bougaev, Brian Mariner, Joshua Walter:
Estimation of Architectural Vulnerability Factors for Discrimination of Single Event Upsets in Cache Memory. CDES 2005: 11-20
Circuit & Functional Design
- Waleed K. Al-Assadi, Pavankumar Chandrasekhar, Bonita Bhaskaran:
Fault Modeling and Testability of CMOS Domino Circuits. CDES 2005: 21-27 - Daniel R. Blum, Mitchell J. Myjak, José G. Delgado-Frias:
Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS. CDES 2005: 28-34 - Bonita Bhaskaran, Venkat Satagopan, Scott C. Smith:
High-Speed Energy Estimation for Delay-Insensitive Circuits. CDES 2005: 35-41 - Derek Nowrouzezahrai, Brian Decker, William Bishop:
High-Performance Double-Precision Cosine Generation. CDES 2005: 42-48 - Eugin Hyun, Kyo-Yong Han, Kwang-Su Seong:
Design of PCI 2.2 Target Controller to Support Prefetch Request. CDES 2005: 49-58
Network, Communication, & Image Processing
- Koert Vlaeminck, Tim Stevens, Wim Van de Meerssche, Filip De Turck, Bart Dhoedt, Piet Demeester:
Implementation of Network Systems Using Network Processor Technology: Performance Evaluation. CDES 2005: 59-63 - Lubomir Ivanov:
Modeling and Verification of a Distributed Transmission Protocol. CDES 2005: 64-70 - Eugin Hyun, Kwang-Su Seong:
Design and Verification of I/O Controller for Future Communication System. CDES 2005: 71-77 - Bonita Bhaskaran, Venkat Satagopan, Waleed K. Al-Assadi, Scott C. Smith:
Implementation of Design For Test for Asynchronous NCL Designs. CDES 2005: 78-84 - Himanshu Thapliyal, M. B. Srinivas, Rameshwar Rao, Hamid R. Arabnia:
Verilog Coding Style for Efficient Synthesis In FPGA. CDES 2005: 85-90
VLSI & SoC: Technology & Applications
- Hector Arteaga, Hussain Al-Asaad:
On Increasing the Observability of Modern Microprocessors. CDES 2005: 91-96 - Jin Liu, José G. Delgado-Frias:
DAMQ Self-Compacting Buffer Schemes for Systems with Network-On-Chip. CDES 2005: 97-103 - Yil Suk Yang, Tae Moon Roh, Dae Woo Lee, Woo Hyun Kwon, Jongdae Kim:
On-Chip Split Shared Data Bus Architecture for SoC. CDES 2005: 104-108 - Waleed Al-Assadi, Thomas Dick:
Design for Test Methodology for the IBM PowerPC 440 Embedded Core. CDES 2005: 109-114
Modeling, Simulation, & Verification
- Anshul Singh, Scott C. Smith:
Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation. CDES 2005: 115-121 - David A. Zier, Jarrod A. Nelson, Ben Lee:
NetSin: An Object-Oriented Architectural Simulator Suite. CDES 2005: 122-128 - Hussain Al-Asaad, Ganesh Valliappan, Lourdes Ramirez:
A Novel Functional Testing and Verification Technique for Logic Circuits. CDES 2005: 129-135 - Jaafar Alghazo, Nazeih Botros:
Modeling and Synthesis of a Modified Floating Point Fused Multiply-Add (FMA) Arithmetic Unit Using VHDL and FPGAs. CDES 2005: 136-142 - Arun Vijayaraghavan, M. Kannan, R. Seshasayanan:
Simulation Analysis of Low Power Synchronous Token Ring Based VLIW processor under GALS Multi-processor technology with improved efficiency. CDES 2005: 143-152
Computer System: Architecture, Design Methodology, & Implementation
- Jinwoo Kim, Kiran Puttaswamy:
Possibility and Limitation of a Hardware-Assisted Data Prefetching Framework Using Off-Line Training of Markovian Predictors. CDES 2005: 153-158 - Mitchell J. Myjak, José G. Delgado-Frias:
A Symmetric Differential Clock Generator for Bit-Serial Hardware. CDES 2005: 159-164 - Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
Design for A Fast And Low Power 2's Complement Multiplier. CDES 2005: 165-167 - Yukinori Sato, Ken-ichi Suzuki, Tadao Nakamura:
An Operand Status Based Instruction Steering Scheme for Clustered Architectures. CDES 2005: 168-174 - Martin Uhl:
On Operating System Basic Building Blocks. CDES 2005: 175-184
Algorithm, Scheduling, & Performance Technologies
- Daniel Pittman, Dennis Edwards:
Space and Time Efficient Lottery Scheduling. CDES 2005: 185-190 - Suryanarayana Tatapudi, José G. Delgado-Frias:
A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme. CDES 2005: 191-197 - Chung-Chin Luo, Yuan-Shin Hwang, Gene Eu Jan:
Minimal Steiner Trees in X Architecture with Obstacles. CDES 2005: 198-203 - Wei-Hao Chiao, Tsung-Hsi Weng, Jean Jyh-Jiun Shann, Chung-Ping Chung, Jimmy Lu:
Low-Power Data Address Bus Encoding Method. CDES 2005: 204-210 - Yau-Chong Hu, Wei-Hau Chiao, Jean Jyh-Jiun Shann, Chung-Ping Chung, Wen-Feng Chen:
Low-Power Branch Prediction. CDES 2005: 211-217 - Jiann-Shiun Yuan, Jia Di:
Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers. CDES 2005: 218-223 - Viktor Bunimov, Manfred Schimmler:
Completely Redundant Modular Exponentiation by Operand Changing. CDES 2005: 224-232
Late Papers
- Alexander Usynin, J. Wesley Hines:
Use of Kernel (Regression) Based Methods for Sensor Validation. CDES 2005: 233-239 - Kenny C. Gross, Eugenio Schuster:
Spectral Decomposition and Reconstruction of Telemetry Signals from Enterprise Computing Systems. CDES 2005: 240-246 - Kalyan Vaidyanathan, Kenny C. Gross:
Monte Carlo Simulation For Optimized Sensitivity of Online Proactive Fault Monitoring Schemes. CDES 2005: 247-252 - Hsun-Jung Cho, Ming-Te Tseng:
A System-on-Chip Approach to Intelligent Traffic Signal Control. CDES 2005: 253-
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