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ORCID35th DAC 1998: San Francico, California, USA
- Basant R. Chawla, Randal E. Bryant, Jan M. Rabaey:
Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998. ACM Press 1998, ISBN 0-89791-964-5
Executive Plenary Panel
- Thomas Pennino:
Customers, Vendors, and Universities: Determining the Future of EDA Together (Panel). 1
Interfaces for Design Reuse
- Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev:
Asynchronous Interface Specification, Analysis and Synthesis. 2-7 - Roberto Passerone, James A. Rowson, Alberto L. Sangiovanni-Vincentelli:
Automatic Synthesis of Interfaces Between Incompatible Protocols. 8-13 - James Smith, Giovanni De Micheli:
Automated Composition of Hardware Components. 14-19
Analog and Mixed-Signal Design Tools
- Mike Chou, Jacob White:
Multilevel Integral Equation Methods for the Extraction of Substrate Coupling Parameters in Mixed-Signal IC's. 20-25 - Alper Demir, Amit Mehrotra, Jaijeet S. Roychowdhury:
Phase Noise in Oscillators: A Unifying Theory and Numerical Methods for Characterisation. 26-31 - Luigi Carro, Marcelo Negreiros
:
Efficient Analog Test Methodology Based on Adaptive Algorithms. 32-37 - Bogdan G. Arsintescu, Edoardo Charbon, Enrico Malavasi, Umakanta Choudhury, William H. Kao:
General AC Constraint Transformation for Analog ICs. 38-43
University Design Contest
- Jacob J. Rael, Ahmadreza Rofougaran, Asad A. Abidi:
Design Methodology Used in a Single-Chip CMOS 900 MHz Spread-Spectrum Wireless Transceiver. 44-49 - Jörg Hilgenstock, Klaus Herrmann, Jan Otterstedt, Dirk Niggemeyer, Peter Pirsch:
A Video Signal Processor for MIMD Multiprocessing. 50-55 - Jens Peter Wittenburg, Willm Hinrichs, Johannes Kneip, Martin Ohmacht, Mladen Berekovic, Hanno Lieske, Helge Kloos, Peter Pirsch:
Realization of a Programmable Parallel DSP for High Performance Image Processing Applications. 56-61 - Roy A. Sutton, Vason P. Srini, Jan M. Rabaey:
A Multiprocessor DSP System Using PADDI-2. 62-65 - A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic:
Design and Implementation of the NUMAchine Multiprocessor. 66-69
Embedded System Design and Exploration
- James Shin Young, Josh MacDonald, Michael Shilman, Abdallah Tabbara, Paul N. Hilfinger, A. Richard Newton:
Design and Specification of Embedded Systems in Java Using Successive, Formal Refinement. 70-75 - Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Miguel Miranda, Kris Croes, Sven Wuytack, Gjalt G. de Jong, Francky Catthoor, Diederik Verkest, Paul Six, Hugo De Man:
Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer. 76-81 - Ireneusz Karkowski, Henk Corporaal:
Design Space Exploration Algorithm for Heterogeneous Multi-Processor Embedded System Design. 82-87 - Pai H. Chou, Gaetano Borriello:
Modal Processes: Towards Enhanced Retargetability Through Control Composition of Distributed Embedded Systems. 88-93
Taming Noise in Deep-Submicron Digital Designs
- Kenneth L. Shepard:
Design Methodologies for Noise in Digital Integrated Circuits. 94-99 - N. S. Nagaraj, Kenneth L. Shepard, Takahide Inone:
Taming Noise in Deep Submicron Digital Integrated Circuits (Panel). 100-101
Control and Data Driven High Level Synthesis
- Ganesh Lakshminarayana, Niraj K. Jha:
FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions. 102-107 - Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. 108-113 - Shantanu Tarafdar, Miriam Leeser:
The DT-Model: High-Level Synthesis Using Data Transfers. 114-117 - Moonwook Oh, Soonhoi Ha:
Rate Optimal VLSI Design from Data Flow Graph. DAC 1998: 118-121
Synthesis Flow in Deep Submicro Technologies
- Ralph H. J. M. Otten, Robert K. Brayton:
Planning for Performance. 122-127 - Amir H. Salek, Jinan Lou, Massoud Pedram:
A DSM Design Flow: Putting Floorplanning, Technology-Napping, and Gate-Placement Together. 128-134
Environment for Collaborative Design
- Peter R. Sutton, Stephen W. Director:
Framework Encapsulations: A New Approach to CAD Tool Interoperability. 134-139 - Ken Hines, Gaetano Borriello:
A Geographically Distributed Framework for Embedded System Design and Validation. 140-145 - Francis L. Chan, Mark D. Spiller, A. Richard Newton:
WELD - An Environment for Web-based Electronic Design. 146-151
New Methods in Functional Verification
- Farzan Fallah, Srinivas Devadas, Kurt Keutzer:
OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification. 152-157 - Raanan Grinwald, Eran Harel, Michael Orgad, Shmuel Ur, Avi Ziv:
User Defined Coverage - A Tool Supported Methodology for Design Verification. 158-163 - Joshua Marantz:
Enhanced Visibility and Performance in Functional Verification by Reconstruction. 164-169 - Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park, Chong-Min Kyung:
Virtual Chip: Making Functional Models Work on Real Target Systems. 170-173
Panel
- Peter Heller:
Hardware/Software Co-Design: The Next Embedded System Design Challenge (Panel). 174-175
System-Level Power Optimization
- Inki Hong, Darko Kirovski, Gang Qu, Miodrag Potkonjak, Mani B. Srivastava:
Power Optimization of Variable Voltage Core-Based Systems. 176-181 - Giuseppe A. Paleologo, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli:
Policy Optimization for Dynamic Power Management. 182-187 - Yanbing Li, Jörg Henkel:
A Framework for Estimation and Minimizing Energy Dissipation of Embedded HW/SW Systems. 188-193
Boolean Methods
- Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi:
Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability. 194-199 - Rolf Drechsler, Nicole Drechsler, Wolfgang Günther:
Fast Exact Minimization of BDDs. 200-205 - Uwe Hinsberger, Reiner Kolla:
Boolean Matching for Large Libraries. 206-211
Extraction and Modeling for Interconnect
- Weiping Shi, Jianguo Liu, Naveen Kakani, Tiejun Yu:
A Fast Hierarchical Algorithm for 3-D Capacitance Extraction. 212-217 - E. Aykut Dengi, Ronald A. Rohrer:
Boundary Element Method Macromodels for 2-D Hierachical Capacitance Extraction. 218-223 - Jinsong Zhao, Wayne Wei-Ming Dai, Sharad Kapur, David E. Long:
Efficient Three-Dimensional Extraction Based on Static and Full-Wave Layered Green's Functions. 224-229
Processor Design and Simulation
- Nevine Nassif, Madhav P. Desai, Dale H. Hall:
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor. 230-235 - Robert M. McGraw, James H. Aylor, Robert H. Klenke:
A Top-Down Design Environment for Developing Pipelined Datapaths. 236-241 - Rita Yu Chen, Robert Michael Owens, Mary Jane Irwin, Raminder Singh Bajwa:
Validation of an Architectural Level Power Analysis Technique. 242-245 - Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura:
Design Methodology of a 200MHz Superscalar Microprocessor: SH-4. 246-249
Panel
- Stephan Ohr:
How Much Analog Does a Designer Need to Know for Successful Mixed-Signal Design? (Panel). 250
Performance Modeling and Characterization for Embedded Systems
- Gustavo de Veciana, Margarida F. Jacome, Jian-Huei Guo:
Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance. 251-256 - Asawaree Kalavade, Pratyush Moghé:
A Tool for Performance Estimation of Networked Embedded End-systems. 257-262 - Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta:
Rate Derivation and Its Applications to Reactive, Real-Time Embedded Systems. 263-268
Advances in Placement and Partitioning
- Hans Eisenmann, Frank M. Johannes:
Generic Global Placement and Floorplanning. 269-274 - Phiroze N. Parakh, Richard B. Brown, Karem A. Sakallah:
Congestion Driven Quadratic Placement. 275-278 - Maogang Wang, Prithviraj Banerjee, Majid Sarrafzadeh:
Potential-NRG: Placement with Incomplete Data. 279-282 - Wen-Jong Fang, Allen C.-H. Wu:
Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication. 283-286 - Jaewon Oh, Massoud Pedram:
Multi-Pad Power/Ground Network Design for Uniform Distribution of Ground Bounce. 287-290
Parasitic Device Extraction and Interconnect Modeling
- Tong Li, Sung-Mo Kang:
Layout Extraction and Verification Methodology CMOS I/O Circuits. 291-296 - Nuno Alexandre Marques, Mattan Kamon, Jacob White, Luís Miguel Silveira:
A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects. 297-302 - Byron Krauter, Sharad Mehrotra:
Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis. 303-308
Design Optimization for DSP
- Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey:
A Methodology for Guided Behavioral-Level Optimization. 309-314 - Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens:
A Programming Environment for the Design of Complex High Speed ASICs. 315-320 - Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith:
Media Architecture: General Purpose vs. Multiple Application-Specific Programmable Processor. 321-326
Panel
- Randal E. Bryant, Gerry Musgrave:
User Experience with High Level Formal Verification (Panel). 327
Bridging the Gap Between Simulation and Formal Verification
- David L. Dill:
What's Between Simulation and Formal Verification? (Extended Abstract). 328-329
Logic Optimization
- Jason Cong, Chang Wu:
Optimal FPGA Mapping and Retiming with Efficient Initial State Computation. 330-335 - Victor N. Kravets, Karem A. Sakallah:
M32: A Constructive multilevel Logic Synthesis System. 336-341 - Shih-Chieh Chang, David Ihsin Cheng:
Efficient Boolean Division and Substitution. 342-347 - Yuji Kukimoto, Robert K. Brayton, Prashant Sawkar:
Delay-Optimal Technology Mapping by DAG Covering. 348-351 - David S. Kung:
A Fast Fanout Optimization Algorithm for Near-Continuous Buffer Libraries. 352-355
Routing for Performance and Crosstalk
- Jason Cong, Patrick H. Madden:
Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs. 356-361 - Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
Buffer Insertion for Noise and Delay Optimization. 362-367 - John Lillis, Premal Buch:
Table-Lookup Methods for Improved Performance-Driven Routing. 368-373 - Hai Zhou, D. F. Wong:
Global Routing with Crosstalk Constraints. 374-377 - Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen:
Timing and Crosstalk Driven Area Routing. 378-381
Practical Optimization Methodologies for High Performance Design
- Arun N. Lokanathan, Jay B. Brockman:
Process Multi-Circuit Optimization. 382-387 - Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David T. Blaauw:
Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. 388-391 - Julian Culetu, Chaim Amir, John MacDonald:
A Practical Repeater Insertion Method in High Speed VLSI Circuits. 392-395 - Paolo Ienne, Alexander Grießing:
Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts? 396-401 - Michael Orshansky, James C. Chen, Chenming Hu:
A Statistical Performance Simulation Methodology for VLSI Circuits. 402-407
RF IC design Methodology
- Behzad Razavi:
RF IC Design Challenges. 408-413 - Al Dunlop, Alper Demir, Peter Feldmann, Sharad Kapur, David E. Long, Robert C. Melville, Jaijeet S. Roychowdhury:
Tools and Methodology for RF IC Design. 414-420 - Frank Y. Yuan:
Electromagnetic Modeling and Signal Integrity Simulation of Power/Ground Networks in High Speed Digital Packages and Printed Circuit Boards. 421-426
Theory and Practice in High Level Synthesis
- Darko Kirovski, Miodrag Potkonjak:
Efficient Coloring of a Large Spectrum of Graphs. 427-432 - Taewhan Kim, William Jao, Steven W. K. Tjiang:
Arithmetic Optimization Using Carry-Save-Adders. 433-438 - Ganesh Lakshminarayana, Niraj K. Jha:
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions. 439-444
BDD Approximation Techniques
- Kavita Ravi, Kenneth L. McMillan, Thomas R. Shiple, Fabio Somenzi:
Approximation and Decomposition of Binary Decision Diagrams. 445-450 - Shankar G. Govindaraju, David L. Dill, Alan J. Hu, Mark Horowitz:
Approximate Reachability with BDDs Using Overlapping Projections. 451-456 - Abelardo Pardo, Gary D. Hachtel:
Incremental CTL Model Checking Using BDD Subsetting. 457-462
Interconnect Modeling and Timing Simulation
- Rony Kay, Lawrence T. Pileggi:
PRIMO: Probability Interpretation of Moments for Delay Calculation. 463-468 - Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas:
ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models. 469-472 - Fang-Jou Liu, Chung-Kuan Cheng:
Extending Moment Computation to 2-Port Circuit Representations. 473-476 - Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov:
Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation. 477-482
Low Power Design Using Multiple Thresholds and Supplies
- Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda:
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. 483-488 - Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De:
Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. 489-494 - James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan:
MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns. 495-500
Panel
- A. Richard Newton:
Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel). 501
Software Synthesis and Retargetable Compilation
- Bill Lin:
Software Synthesis of Process-Based Concurrent Programs. 502-505 - Youpyo Hong, Peter A. Beerel, Luciano Lavagno, Ellen Sentovich:
Don't Care-Based BDD Minimization for Embedded Software. 506-509 - Silvina Hanono, Srinivas Devadas:
Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. 510-515 - Haris Lekatsas, Wayne H. Wolf:
Code Compression for Embedded Systems. 516-521
Formal Methods in Functional Verification
- Clark W. Barrett, David L. Dill, Jeremy R. Levitt:
A Decision Procedure for Bit-Vector Arithmetic. 522-527 - Farzan Fallah, Srinivas Devadas, Kurt Keutzer:
Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability. 528-533 - Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy:
Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation. 534-537 - Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger:
Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment. 538-541
Core Test and BIST
- Indradeep Ghosh, Sujit Dey, Niraj K. Jha:
A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. 542-547 - Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Introducing Redundant Computations in a Behavior for Reducing BIST Resources. 548-553 - Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik:
A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. 554-559
Interconnect Analysis and Reliability in Deep Sub-Micron
- Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Figures of Merit to Characterize the Importance of On-Chip Inductance. 560-565 - Yehia Massoud, Steve S. Majors, Tareq Bustami, Jacob K. White:
Layout Techniques for Minimizing On-Chip Interconnect Self Inductance. 566-571 - N. S. Nagaraj, Frank Cano, Haldun Haznedar, Duane Young:
A Practical Approach to Static Signal Electromigration Analysis. 572-577
Panel
- Carlos Dangelo:
Design Productivity: How To Measure It, How To Improve It (Panel). 578-579
Timing Analysis
- Yuji Kukimoto, Robert K. Brayton:
Hierarchical Functional Timing Analysis. 580-585 - Tod Amon, Gaetano Borriello, Jiwen Liu:
Making Complex Timing Relationships Readable: Presburger Formula Simplicication Using Don't Cares. 586-590 - Mahadevamurty Nemani, Farid N. Najm:
Delay Estimation VLSI Circuits from a High-Level View. 591-594 - Florentin Dartu, Lawrence T. Pileggi:
TETA: Transistor-Level Engine for Timing Analysis. 595-598
New Techniques in State Space Explorations
- C. Han Yang, David L. Dill:
Validation with Guided Search of the State Space. 599-604 - Aiguo Xie, Peter A. Beerel:
Efficient State Classification of Finite State Markov Chains. 605-610 - Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee:
An Implicit Algorithm for Finding Steady States and its Application to FSM Verification. 611-614 - Adnan Aziz, James H. Kukula, Thomas R. Shiple:
Hybrid Verification Using Saturated Simulation. 615-618
Advanced ATPG Techniques
- Dechang Sun, Bapiraju Vinnakota, Wanli Jiang:
Fast State Verification. 619-624 - Aiman H. El-Maleh, Mark Kassab, Janusz Rajski:
A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. 625-631 - Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu:
Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. 632-637
Practical Experience of Funtional Verification for Complex ICs
- Scott A. Taylor, Michael Quinn, Darren Brown, Nathan Dohm, Scot Hildebrandt, James Huggins, Carl Ramey:
Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor - The DEC Alpha 21264 Microprocessor. 638-643 - Yossi Malka, Avi Ziv:
Design Reliability - Estimation through Statistical Analysis of Bug Discovery Data. 644-649 - Adrian Evans, Allan Silburt, Gary Vrckovnik, Thane Brown, Mario Dufresne, Geoffrey Hall, Tung Ho, Ying Liu:
Functional Verification of Large ASICs. 650-655
Panel
- Erach Desai:
The EDA Start-up Experience: The First Product (Panel). 656-657
Fast Functiona Simulation
- Kunle Olukotun, Mark A. Heinrich, David Ofelt:
Digital System Simulation: Methodologies and Examples. 658-663 - Yufeng Luo, Tjahjadi Wongsonegoro, Adnan Aziz:
Hybrid Techniques for Fast Functional Simulation. 664-667 - Jerry Bauer, Michael Bershteyn, Ian Kaplan, Paul Vyedin:
A Reconfigurable Logic Machine for Fast Event-Driven Simulation. 668-671
Power Estimation and Modeling
- Victor Kim, Prithviraj Banerjee:
Parallel Algorithms for Power Estimation. 672-677 - Zhanping Chen, Kaushik Roy:
A Power Macromodeling Technique Based on Power Sensitivity. 678-683 - Qinru Qiu, Qing Wu, Massoud Pedram:
Maximum Power Estimation Using the Limiting Distributions of Extreme Order Statistics. 684-689 - Byunggyu Kwak, Eun Sei Park:
An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic Circuits. 690-693 - Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira:
Using Complementation and Resequencing to Minimize Transitions. 694-697
Technology Mapping for Programmable Logic
- Jason Helge Anderson, Stephen Dean Brown:
Technology Mapping for Large Complex PLDs. 698-703 - Jason Cong, Songjie Xu:
Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs. 704-707 - Madhukar R. Korupolu, K. K. Lee, D. F. Wong:
Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs. 708-711 - Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang:
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. 712-717 - Balakrishna Kumthekar, Luca Benini, Enrico Macii, Fabio Somenzi:
In-Place Power Optimization for LUT-Based FPGAs. 718-721 - Jan-Min Hwang, Feng-Yi Chiang, TingTing Hwang:
A Re-engineering Approach to Low Power FPGA Design Using SPFD. 722-725
Power Dissipation and Distribution in High Performance Processors
- Michael K. Gowan, Larry L. Biro, Daniel B. Jackson:
Power Considerations in the Design of the Alpha 21264 Microprocessor. 726-731 - Vivek Tiwari, Deo Singh, Suresh Rajgopal, Gaurav Mehta, Rakesh Patel, Franklin Baez:
Reducing Power in High-Performance Microprocessors. 732-737 - Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden:
Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. 738-743 - Gregory Steele, David Overhauser, Steffen Rochel, Syed Zakir Hussain:
Full-Chip Verification Methods for DSM Power Distribution Systems. 744-749
Challenge in the Test on System-On-A-Chip Era
- Prab Varma:
System Chip Test Challenges, Are There Solutions Today? (Panel). 750-751 - Yervant Zorian:
System-Chip Test Strategies (Tutorial). 752-757
Controller Decomposition for Power and Area Minimization
- José C. Monteiro, Arlindo L. Oliveira:
Finite State Machine Decomposition For Low Power. 758-763 - Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino:
Computational Kernels and their Application to Sequential Power Optimization. 764-769 - Andrew Seawright, Wolfgang Meyer:
Partitioning and Optimizing Controllers Synthesized from Hierarchical High-Level Descriptions. 770-775
IT Protection Technologies
- Andrew B. Kahng, John C. Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe:
Watermarking Techniques for Intellectual Property Protection. 776-781 - Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe:
Robust IP Watermarking Methodologies for Physical Design. 782-787 - Scott Hauck, Stephen Knol:
Data Security for Web-based CAD. 788-793
Case Studies of New Design Methods
- Ulrich Holtmann, Peter Blinzer:
Design of a SPDIF Receiver Using Protocol Compiler. 794-799 - Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-Won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Kyu Ho Park, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung:
MetaCore: An Application Specific DSP Development System. 800-803 - Tullio Cuatto, Claudio Passerone, Luciano Lavagno, Attila Jurecska, Antonino Damiano, Claudio Sansoè, Alberto L. Sangiovanni-Vincentelli:
A Case Study in Embedded System Design: An Engine Control Unit. 804-807 - Thomas W. Albrecht, Johann Notbauer, Stefan Rohringer:
HW/SW CoVerification Performance Estimation and Benchmark for a 24 Embedded RISC Core Design. 808-811 - Daniel Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong:
System-level exploration with SpecSyn. 812-817
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