DATE 1998: Paris, France

Design Optimization of Building Blocks

HW/SW Partitioning and Communication Synthesis

Asynchronous and Hybrid VHDL-Based Design

Data Path and FPGA Testing

Design Methods for High Performance Applications

Scheduling in Embedded Systems

Advanced Techniques for VHDL Design

Novel BIST Approaches

Architectures for Image Processing

Scheduling and Analysis of HW/SW

Extensions to VHDL

Error Detection and Design Validation

IP Based System-on-a-Chip Design

Design Reuse Methodologies

Flat and Timing-Driven Processor Design

Reconfigurable Systems

Digital Simulation and Estimation

Synthesis of Reprogrammable and Reconfigurable Architectures

Partitioning and Routing

Panel - Formal Verification: A New Standard CAD Tool for the Industrial Design Flow

Simulation for High-Level Design

Architectural Synthesis

Timing and Crosstalk in Interconnect

Panel: Next Generation System Design Tools

IDDQ and Memory Testing

Microsystems

Interconnect Modeling

Design for Manufacturability - Embedded Tutorial

Sequential Circuit Testing

Issues in Behavioral Synthesis

Formal Equivalence Checking Using Decision Diagrams

Silicon Debug of Systems-on-Chips

Characterization and Verification of Analogue Circuits

Benchmark Circuits, Technology Mapping and Scan Chains

Physical to Gate Level Design for Low-Power

Embedded Memory and Embedded Logic

Analogue Circuit Modeling and Design Methodology

Combinational Logical Synthesis

High Level Power Estimation

Petri Nets and Dedicated Formalisms

Mixed-Signal Test and DFT

Sequential Logic Synthesis

High-Level Power Optimization

System Architecture Design

Simulation and Test Tools for Analogue Circuits

Poster Session