Stop the war!

Остановите войну!

• solidarity - (ua) - (ru)
• news - (ua) - (ru)
• donate - donate - donate

for scientists:

• ERA4Ukraine
• Assistance in Germany
• Ukrainian Global University
• #ScienceForUkraine

default search action

• combined dblp search
• author search
• venue search
• publication search

Authors:

• no matches

• 

Venues:

• no matches

• 

Publications:

• no matches

• 

ask others

• Google
• Google Scholar
• Semantic Scholar
• Internet Archive Scholar
• CiteSeerX
• ORCID

Refine list

refinements active!

zoomed in on ?? of ?? records

dismiss all constraints

view refined list in

dblp search

export refined list as

XML

JSON

JSONP

BibTeX

showing all ?? records

• 
  2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France. IEEE Computer Society 2004, ISBN 0-7695-2085-5

Volume 1 - 2 - Designers Forum

• 
  Robert C. Aitken, Fidel Muradali:
  From Working Design Flow to Working Chips: Dependencies and Impacts of Methodology Decisions. 2
• 
  Veikko Loukusa, Helena Pohjonen, Antti Ruha, Tarmo Ruotsalainen, Olli Varkki:
  Systems on Chips Design: System Manufacturer Point of View. 3-4
• 
  Sanjay Dandia:
  Package Design for High Performance ICs. 5
• 
  Bill Eklow:
  IP Testing - The Future Differentiator? 6-9

• 
  Adão Antônio de Souza Jr., Luigi Carro:
  Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCs. 10-15
• 
  Faress Tissafi-Drissi, Ian O'Connor, Frédéric Gaffiot:
  RUNE: Platform for Automated Design of Integrated Multi-Domain Systems. Application to High-Speed CMOS Photoreceiver Front-Ends. 16-21
• 
  Yiming Chen, Xiaojuen Yuan, David Scagnelli, James Mecke, Jeff Gross, David L. Harame:
  Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS Technology. 22-27
• 
  Peter H. Saul:
  Low Power Analogue 90 Degree Phase Shifter. 28-33
• 
  Pavel Horsky:
  A 16 Bit + Sign Monotonic Precise Current DAC for Sensor Applications. 34-38
• 
  Sotiris Bantas, Yorgos Koutsoyannopoulos, Apostolos Liapis:
  An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain. 39-45

• 
  Andreas Wortmann, Sven Simon, Matthias Müller:
  A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core. 46-51
• 
  Alex Panato, Sandro V. Silva, Flávio Rech Wagner, Marcelo O. Johann, Ricardo Reis, Sergio Bampi:
  Design of Very Deep Pipelined Multipliers for FPGAs. 52-57
• 
  Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane, Michel Langevin, Damien Lyonnard:
  Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding. 58-63
• 
  A. P. Niranjan, Paul C. Wiscombe:
  Islands of Synchronicity, a Design Methodology for SoC Design. 64-69
• 
  Luigi Dadda, Marco Macchetti, Jeff Owen:
  The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512). 70-75
• 
  Chang Hong Lin, Yuan Xie, Wayne H. Wolf:
  LZW-Based Code Compression for VLIW Embedded Systems. 76-81
• 
  Rocco Le Moigne, Olivier Pasquier, Jean Paul Calvez:
  A Generic RTOS Model for Real-time Systems Simulation with SystemC. 82-87
• 
  Mauro Cocco, John Dielissen, Marc J. M. Heijligers, Andries Hekstra, Jos Huisken:
  A Scalable Architecture for LDPC Decodin. 88-95

• 
  Stephen Schmitt, Wolfgang Rosenstiel:
  Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments. 96-101
• 
  Alexander Krupp, Wolfgang Müller, Ian Oliver:
  Formal Refinement and Model Checking of an Echo Cancellation Unit. 102-107
• 
  Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk:
  Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip. 108-113
• 
  Tobias Thiel:
  Have I Really Met Timing? - Validating PrimeTime Timing Reports with Spice. 114-119
• 
  Vlado Vorisek, Thomas Koch, Hermann Fischer:
  At-Speed Testing of SOC ICs. 120-125
• 
  Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin:
  Utilizing Formal Assertions for System Design of Network Processors. 126-133

• 
  Juan C. Diaz, Marta Saburit:
  Clock Management in a Gigabit Ethernet Physical Layer Transceiver Circuit. 134-139
• 
  Richard Auletta:
  Expert System Perimeter Block Placement Floorplanning. 140-143
• 
  Ibrahim M. Elfadel, Alina Deutsch, Gerard V. Kopcsay, Bradley Rubin, Howard H. Smith:
  A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses. 144-149
• 
  Jesús Ruiz-Amaya, Josep Lluís de la Rosa, Fernando Medeiro, Francisco V. Fernández, Rocío del Río, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez:
  MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time [Sigma, Delta] Modulators. 150-155
• 
  Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl:
  RTL Processor Synthesis for Architecture Exploration and Implementation. 156-160
• 
  Ankush Varma, Shuvra S. Bhattacharyya:
  Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems. 161-167

• 
  Franco Fummi, Stefano Martini, Giovanni Perbellini, Massimo Poncino, Fabio Ricciato, Maura Turolla:
  Heterogeneous Co-Simulation of Networked Embedded Systems. 168-173
• 
  Marcello Coppola, Stephane Curaba, Miltos D. Grammatikakis, Giuseppe Maruccia, Francesco Papariello:
  OCCN: A Network-On-Chip Modeling and Simulation Framework. 174-179
• 
  Francesco Bruschi, Massimo Bombana:
  A Design Methodology for the Exploitation of High Level Communication Synthesis. 180-185
• 
  Ioannis Papaefstathiou, George Kornaros, Nicholaos Zervos:
  Software Processing Performance in Network Processors. 186-191
• 
  Friedbert Berens, Gerd Kreiselmaier, Norbert Wehn:
  Channel Decoder Architecture for 3G Mobile Wireless Terminals. 192-197
• 
  César Albenes Zeferino, Márcio Eduardo Kreutz, Altamiro Amadeu Susin:
  RASoC: A Router Soft-Core for Networks-on-Chip. 198-205

• 
  Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese:
  Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware. 206-211
• 
  Hala A. Farouk, Magdy Saeb:
  Design and Implementation of a Secret Key Steganographic Micro-Architecture Employing FPGA. 212-217
• 
  Daniel Ferrer, Ramiro González, Roberto Fleitas, Julio Pérez Acle, Rafael M. Canetti:
  NeuroFPGA - Implementing Artificial Neural Networks on Programmable Logic Devices. 218-223
• 
  Roger Endrigo Carvalho Porto, Luciano Volcan Agostini:
  Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation. 224-229
• 
  Marc Quax, Jos Huisken, Jef L. van Meerbergen:
  A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver. 230-235
• 
  W. W. S. Chu, Robert G. Dimond, S. Perrott, S. P. Seng, Wayne Luk:
  Customisable EPIC Processor: Architecture and Tools. 236-241
• 
  Marcos R. Boschetti, Ivan Saraiva Silva, Sergio Bampi:
  A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications. 242-247
• 
  Djones Lettnin, Axel G. Braun, Martin Bogdan, Joachim Gerlach, Wolfgang Rosenstiel:
  Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks. 248-255

• 
  Sara Blanc, Joaquin Gracia, Pedro J. Gil:
  Experiences during the Experimental Validation of the Time-Triggered Architecture. 256-261
• 
  Thorsten Schubert, Jürgen Hanisch, Joachim Gerlach, Jens-E. Appell, Wolfgang Nebel:
  Evaluation of a Refinement-Driven SystemC'-Based Design Flow. 262-267
• 
  Nico Bannow, Karsten Haug:
  Evaluation of an Object-Oriented Hardware Design Methodology for Automotive Applications. 268-273
• 
  W. J. Bainbridge, Luis A. Plana, Stephen B. Furber:
  The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip. 274-279
• 
  Beibei Ren, Anru Wang, Joyopriya Bakshi, Kai Liu, Wei Li, Wayne Wei-Ming Dai:
  A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications. 280-285
• 
  Jay Abraham, Guruprasad Rao:
  Qualification and Integration of Complex I/O in SoC Design Flows. 286-293

• 
  Lieven Hollevoet, Andy Dewilde, Kristof Denolf, Francky Catthoor, Filip Louagie:
  A Power Optimized Display Memory Organization for Handheld User Terminal. 294-299
• 
  Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger:
  Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards. 300-305
• 
  Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto:
  Analysis and Modeling of Energy Reducing Source Code Transformations. 306-311
• 
  Francesco Menichelli, Mauro Olivieri, Luca Benini, Monica Donno, Labros Bisdounis:
  A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design. 312-317
• 
  Andrea Bona, Vittorio Zaccaria, Roberto Zafalon:
  System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip. 318-323
• 
  Krisztián Flautner, David Flynn, David Roberts, Dipesh I. Patel:
  IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling. 324-329

• 
  Kathy Werner:
  Can IP Quality be Objectively Measured? 330-331
• 
  Stephen Bailey, Erich Marschner, Jayaram Bhasker, Jim Lewis, Peter J. Ashenden:
  Improving Design and Verification Productivity with VHDL-200x. 332-335
• 
  Pierluigi Daglio, David Iezzi, Danilo Rimondi, Carlo Roma, Salvatore Santapa:
  Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components. 336-337
• 
  B. Hecker, M. Chavassieux, M. Laflutte, E. Beguin, L. Lagasse, Jean Oudinot:
  VHDL-AMS Library Development for Pacemaker Applications. 338-341
• 
  Franco Fummi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino:
  Modeling and Analysis of Heterogeneous Industrial Networks Architectures. 342-344

a service of  

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.

Unpaywalled article links

Add open access links from to the list of external document links (if available).

load links from unpaywall.org

Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.

Archived links via Wayback Machine

For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).

load content from archive.org

Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.

Reference lists

Add a list of references from , , and to record detail pages.

load references from crossref.org and opencitations.net

Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.

Citation data

Add a list of citing articles from and to record detail pages.

load citations from opencitations.net

Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.

OpenAlex data

Load additional information about publications from .

load data from openalex.org

Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.

last updated on 2024-04-18 20:18 CEST by the dblp team

 all metadata released as open data under CC0 1.0 license

see also: Terms of Use | Privacy Policy | Imprint

dblp was originally created in 1993 at:

 

since 2018, dblp has been operated and maintained by:

 

the dblp computer science bibliography is funded and supported by: