Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID14th DDECS 2011: Cottbus, Germany
- Rolf Kraemer, Adam Pawlak, Andreas Steininger, Mario Schölzel, Jaan Raik, Heinrich Theodor Vierhaus:
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011. IEEE Computer Society 2011, ISBN 978-1-4244-9755-3
Keynote Talks
- Raul Camposano:
Design technology and the cloud. 1 - Andrzej J. Strojwas:
Cost effective scaling to 22nm and below technology nodes. 2 - Jürgen Alt:
Future of EDA: Usual suspect or silent hero for successful semiconductor business? 3
Embedded Tutorials
- Bernd Tillack:
SiGe BiCMOS platform - baseline technology for More Than Moore process module integration. 4 - Krishnendu Chakrabarty:
Testing and design-for-testability solutions for 3D integrated circuits. 5 - Karsten Einwich:
Introduction to the SystemC AMS extension standard. 6-8 - Dong S. Ha:
Small scale energy harvesting - principles, practices and future trends. 9
System Design I
- Markus Ferringer:
Conversion and interfacing techniques for asynchronous circuits. 11-16 - Muhammad Aamir Khan, Hans G. Kerkhoff:
A system-level platform for dependability enhancement and its analysis for mixed-signal SoCs. 17-22 - Vipul Chawla, Dong Sam Ha:
Dual use of power lines for data communications in microprocessors. 23-28
Mixed-Signal Design & Test
- Krzysztof Siwiec
, Tomasz Borejko, Witold A. Pleskacz:
PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications. 29-34 - Yolanda Lechuga, Román Mozuelos, Mar Martínez, Salvador Bracho:
Design-for-Test method for high-speed ADCs: Behavioral description and optimization. 35-40 - Sumit Adhikari, Muhammad Farooq, Jan Haase, Christoph Grimm:
High performance adaptive sensor interface design through model based estimation of analog non-idealities. 41-46
IP Design & Verification
- Xuan-Tu Tran, Van-Huan Tran:
Cost-efficient 130nm TSMC Forward Transform and Quantization for H.264/AVC encoders. 47-52 - David Hély, Vincent Beroulle, Feng Lu, José Ramón García Oya:
Towards an unified IP verification and robustness analysis platform. 53-58 - Wlodzimierz Wrona, Pawel Duc, Lukasz Barcik, Wojciech Pietrasina:
An example of DISPLAY-CTRL IP Component verification in SCE-MI based emulation platform. 59-63
Analog Design & Test
- Florian Chouard, Shailesh More, Michael Fulde, Doris Schmitt-Landsiedel:
An analog perspective on device reliability in 32nm high-κ metal gate technology. 65-70 - Daniel Arbet, Juraj Brenkus, Gábor Gyepes, Viera Stopjaková:
Increasing the efficiency of analog OBIST using on-chip compensation of technology variations. 71-74 - Michal Lukaszewicz, Tomasz Borejko, Witold A. Pleskacz:
A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations. 75-79
Fault Diagnosis
- Sergei Kostin, Raimund Ubar, Jaan Raik:
Defect-oriented module-level fault diagnosis in digital circuits. 81-86 - Miroslav Manik, Elena Gramatová:
Efficient diagnostics algorithms for regular computing structures. 87-92 - Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker:
SAT-based analysis of sensitisable paths. 93-98 - Dae Young Lee, David D. Wentzloff, John P. Hayes:
Wireless wafer-level testing of integrated circuits via capacitively-coupled channels. 99-104
Physical Design & Test
- Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen:
Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip. 105-110 - Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
Decoupling capacitance boosting for on-chip resonant supply noise reduction. 111-114 - Tetsuya Iizuka, Kunihiro Asada:
An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator. 115-120 - Aleksandar Simevski, Rolf Kraemer, Milos Krstic:
Low-complexity integrated circuit aging monitor. 121-125
Poster Session I
- Jakub Kopanski, Witold A. Pleskacz, Dariusz Pienkowski:
A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology. 131-134 - Farid Lahrach, Abderrahim Doumar, Eric Châtelet:
Fault tolerance of SRAM-based FPGA via configuration frames. 139-142 - Markus Ulbricht, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus:
A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors. 143-146 - Pawel Dabal, Ryszard Pelka:
A chaos-based pseudo-random bit generator implemented in FPGA device. 151-154 - Pawel Pawlowski, Adam Dabrowski, Piotr Skrzypek, Piotr Roszak, Andrzej Palejko, Tomasz Walenciak, Mateusz Mor:
Software defined radio - design and implementation of complete platform. 155-158 - Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Michel Renovell:
Influence of parasitic memory effect on single-cell faults in SRAMs. 159-162 - Knut Wold, Slobodan Petrovic:
Behavioral model of TRNG based on oscillator rings implemented in FPGA. 163-166 - Oliver Stecklina, Frank Vater, Thomas Basmer, Erik Bergmann, Hannes Menzel:
Hybrid Simulation Environment for rapid MSP430 system design test and validation using MSPsim and SystemC. 167-170 - Tsuyoshi Iwagaki, Kewal K. Saluja:
Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations. 175-178 - Stefan Kolodzinski, Edward Hrynkiewicz:
Decomposition of multi-output logic function in Reed-Muller spectral domain. 179-182
Power Aware Design
- Hagen Sämrow, Claas Cornelius, Philipp Gorski, Jakob Salzmann, Andreas Tockhorn, Dirk Timmermann:
Functional enhancements of TMR for power efficient and error resilient ASIC designs. 183-188 - Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
A study of path delay variations in the presence of uncorrelated power and ground supply noise. 189-194 - Hans Kristian Otnes Berge, Amir Hasanbegovic, Snorre Aunet:
Muller C-elements based on minority-3 functions for ultra low voltage supplies. 195-200 - Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka, Denis Réal:
Power consumption traces realignment to improve differential power analysis. 201-206
Fault Tolerance and Reliability
- Luca Sterpone, Davide Sabena, Salvatore Campagna, Matteo Sonza Reorda:
Fault injection analysis of transient faults in clustered VLIW processors. 207-212 - Michael Augustin, Michael Gössel, Rolf Kraemer:
Implementation of Selective Fault Tolerance with conventional synthesis tools. 213-218 - Tobias Koal, Heinrich Theodor Vierhaus:
Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair. 219-224 - Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf:
An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. 225-230
Hardware/Software Co-Design
- Viktor Pus, Michal Kajan, Jan Korenek:
Hardware architecture for packet classification with prefix coloring. 231-236 - Mihkel Tagel, Peeter Ellervee, Thorsten Hollstein, Gert Jervan:
Communication modelling and synthesis for NoC-based systems with real-time constraints. 237-242 - Ke Jiang, Petru Eles, Zebo Peng:
Optimization of message encryption for distributed embedded systems with real-time constraints. 243-248
Nano-Technology Problems and Solutions
- Carmen Garcia, Antonio Rubio:
Manufacturing variability analysis in Carbon Nanotube Technology: A comparison with bulk CMOS in 6T SRAM scenario. 249-254 - Fabian Hopsch, Michael Lindig, Bernd Straube, Wolfgang Vermeiren:
Characterization of digital cells for statistical test. 255-260 - Martin Wirnshofer, Leonhard Heiß, Georg Georgakos, Doris Schmitt-Landsiedel:
A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring. 261-266
Poster Session II
- Artur Marchlewski, Horst Zimmermann, Ingrid Jonak-Auer, Ewald Wachmann:
Receiver OEIC using a bipolar translinear loop. 267-270 - Stefan Farfeleder, Thomas Moser, Andreas Krall, Tor Stålhane, Herbert Zojer, Christian Panis:
DODT: Increasing requirements formalism using domain ontologies for improved embedded systems development. 271-274 - Yaseen Zaidi, Sumit Adhikari, Christoph Grimm:
Abstract modeling and simulation based selective estimation. 275-278 - Zdenek Prikryl, Jakub Kroustek, Tomas Hruska, Dusan Kolár:
Fast just-in-time translated simulator for ASIP design. 279-282 - Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz:
CAD tool for PLL Design. 283-286 - Damian Modrzyk, Michal Staworko:
Verification of JPEG2000 encoder based on rate and distortion curve analysis. 289-292 - Cinzia Bernardeschi, Luca Cassano, Andrea Domenici:
Failure probability of SRAM-FPGA systems with Stochastic Activity Networks. 293-296 - Liviu Agnola, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan:
Improving performance of robust Self Adaptive Caches by optimizing the switching algorithm. 297-300 - Thilo Ohlemueller, Markus Petri:
Sample synchronization of multiple multiplexed DA and AD converters in FPGAs. 301-304 - Vinay Gautam, Kailash Chandra Ray, Pauline C. Haddow:
Hardware efficient design of Variable Length FFT Processor. 309-312
System Design II
- Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson:
High-performance hardware accelerators for sorting and managing priorities. 313-318 - Jirí Matousek, Pavol Korcek:
Precise IPv4/IPv6 packet generator based on NetCOPE platform. 319-324 - Jiri Tobola, Jan Korenek:
Effective hash-based IPv6 longest prefix match. 325-328
3D Design & Optimisation
- Mottaqiallah Taouil, Said Hamdioui:
Stacking order impact on overall 3D die-to-wafer Stacked-IC cost. 335-340 - Yiorgos I. Bontzios, Michael G. Dimopoulos, Alkis A. Hatzopoulos:
A memetic algorithm for computing 3D capacitance in multiconductor VLSI circuits. 341-346
Memory Design and Test
- Mauricio de Carvalho, Paolo Bernardi, Matteo Sonza Reorda, Nicola Campanelli, Tamas Kerekes, Davide Appello, Mario Barone, Vincenzo Tancorre, Marco Terzi:
Optimized embedded memory diagnosis. 347-352 - Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. 353-358 - Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
On using a SPICE-like TSTAC™ eFlash model for design and test. 359-364 - Elena Ioana Vatajelu, Joan Figueras:
Statistical analysis of 6T SRAM data retention voltage under process variation. 365-370
Logic Design and Test
- Pavel Bartos, Zdenek Kotásek, Jan Dohnal:
Decreasing test time by scan chain reorganization. 371-374 - Xiaoxin Fan, Sudhakar M. Reddy, Irith Pomeranz:
Max-Fill: A method to generate high quality delay tests. 375-380 - Urban Ingelsson, Shih-Yen Chang, Erik Larsson:
Measurement point selection for in-operation wear-out monitoring. 381-386 - Jiri Jenícek, Martin Rozkovec, Ondrej Novák:
Test vector overlapping based compression tool for narrow test access mechanism. 387-392
Poster Session III
- Farhad Goodarzy, Efstratios Skafidas:
A 20 pJ/b (10 µW) digital receiver based on a new modulation (SAS) for retinal prosthesis application. 393-394 - Gábor Gyepes, Juraj Brenkus, Daniel Arbet, Viera Stopjaková:
Comparison of iddt test efficiency in covering opens in SRAMs realised in two different technologies. 395-396 - Martin Straka, Jan Kastil, Jaroslav Novotný, Zdenek Kotásek:
Advanced fault tolerant bus for multicore system implemented in FPGA. 397-398 - Oscar Ruano, Juan Antonio Maestro, Pedro Reviriego:
Validation and optimization of TMR protections for circuits in radiation environments. 399-400 - Vlastimil Kosar, Jan Korenek:
Reduction of FPGA resources for regular expression matching by relation similarity. 401-402 - Jeong-Ki Kim, Jihoon Jeong, Dong Sam Ha, Hyung-Soo Lee:
Low-power quadrature VCO design for medical implant communication service. 403-404 - Lukás Nagy, Viera Stopjaková:
Current sensing methodology for completion detection in self-timed systems. 405-406 - Uros Pesovic, Sinisa Randic, Zoran Stamenkovic:
A wireless ECG sensor node based on Huffman data encoder. 411-412 - Martin Pospisilik, Milan Adamek:
Advanced rectifier and driver for analog VU meter. 413-414
Verification
- Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler:
Automatic property generation for the formal verification of bus bridges. 417-422 - Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik:
Probabilistic equivalence checking based on high-level decision diagrams. 423-428 - Stefan Kupferschmid, Bernd Becker, Tino Teige, Martin Fränzle:
Proof certificates and non-linear arithmetic constraints. 429-434 - Mohamed Bawadekji, Daniel Große, Rolf Drechsler:
TLM protocol compliance checking at the Electronic System Level. 435-440
Reconfigurable Systems
- Muhammad Moazam Azeem, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Error recovery technique for coarse-grained reconfigurable architectures. 441-446 - Richard Ruzicka, Václav Simek, Lukás Sekanina:
Behavior of CMOS polymorphic circuits in high temperature environment. 447-452 - Petr Honzík, Jirí Kadlec:
Dynamic placement applications into Self Adaptive network on FPGA. 453-456 - André Seffrin, Sorin A. Huss:
Minimal physical resource allocation of pi-calculus schedules to dynamically reconfigurable platforms. 457-462
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-19 19:18 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
