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ORCIDEURO-DAC 1990: Glasgow, Scotland, UK
- Gordon Adshead, Jochen A. G. Jess:
European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990. IEEE Computer Society 1990, ISBN 0-8186-2024-2
Tools for testing
- Michael Zimmermann, Manfred Geilert:
Generation of embedded RAMs with built-in test using object-oriented programming. 2-6 - Steve Hodgson, Len Theobald, W. B. Hughes, Richard Illman:
ASTA: an integrated system for bist analysis & automatic test generation. 7-12 - Sybille Hellebrand, Hans-Joachim Wunderlich:
Tools and devices supporting the pseudo-exhaustive test. 13-17 - Martin Klimke, Christian Winkelmeyr, Herbert Eichinger:
Development of test programs with the aid of a testeroriented pattern language. 18-22
Databases and frameworks
- Thomas Kathöfer, W. Fox, D. Nolte, K. Pielsticker, R. Quester, F. Rupprecht, M. Schrewe:
A database interface for phased tool integration. 24-28 - Pieter van der Wolf, Peter Bingley, Patrick M. Dewilde:
On the architecture of a CAD framework: the NELSIS approach. 29-33 - G. W. Sloof, Peter Bingley, Patrick M. Dewilde, T. G. R. M. van Leuken, Pieter van der Wolf:
Design data management in a distributed hardware environment. 34-38 - Jaan Haabma, Bernd Steinmüller:
The NMP-CADLAB framework: a common framework for tool integration and development. 39-43
Formal verification
- Ranga Vemuri
:
On the notion of the normal form register-level structures and its applications in design-space exploration. 46-51 - Hélène Collavizza:
Functional semantics of microprocessors at the microprogram level and correspondence with the machine instruction level. 52-56 - Olivier Coudert, Christian Berthet, Jean Christophe Madre:
Formal boolean manipulations for the verification of sequential machines. 57-61 - Diederik Verkest, Luc J. M. Claesen, Hugo De Man:
Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment. 62-66
Scheduling and allocation I
- Antoine Delaruelle, O. McArdle, Jef L. van Meerbergen, Cees Niessen:
Synthesis of delay functions in DSP compilers. 68-72 - Werner Grass:
A branch-and-bound method for optimal transformation of data flow graphs for observing hardware constraints. 73-77 - Neerav Berry, Barry M. Pangrle:
SCHALLOC: an algorithm for simultaneous scheduling & connectivity binding in a datapath synthesis system. 78-82 - David J. Mallon, Peter B. Denyer:
A new approach to pipeline optimisation. 83-88
Simulation languages
- Daniel Fischer, Yossi Levhari, Gadi Singer:
NETHDL: abstraction of schematics to high-level HDL. 90-96 - C. O. Newton, M. G. Hill:
Comparison of implementations of real arithmetic in ELLA and VHDL. 97-101 - Mart Altmäe:
MINT: a VHDL simulation system. 102-106 - Tuomo Tikkanen, Timo Lappänen, Jorma Kivelä:
Structured analysis and VHDL in embedded ASIC design and verification. 107-111
Cell generators
- Akhilesh Tyagi:
An algebraic model for design space with applications to function module generation. 114-118 - Martin Lefebvre, Chong Chan, Grant Martin:
Transistor placement and interconnect algorithms for leaf cell synthesis. 119-123 - Robi Dutta, Maurice Marks, Craig Morrissey, Ravi Rao, Lee Sapiro:
A flexible hierarchical 3-D module assembler. 124-128 - R. Burgess, C. Wouters:
PARAGON: a new package for gate matrix layout synthesis. 129-134
Scheduling and allocation II
- Ahmed Hemani, Adam Postula:
A neural net based self organising scheduling algorithm. 136-140 - Leon Stok:
Interconnect optimisation during data path allocation. 141-145 - Peter Marwedel:
Matching system and component behaviour in MIMOLA synthesis tools. 146-156 - Raul Camposano, Reinaldo A. Bergamaschi:
Redesign using state splitting. 157-161
Description of design systems and methodologies
- Mehrdad Negahban, Daniel Gajski:
Silicon compilation of switched: capacitor networks. 164-168 - Georges G. E. Gielen, Koen Swings, Willy M. C. Sansen:
An intelligent design system for analogue integrated circuits. 169-173 - Bernd Becker, Thomas Burch, Günter Hotz, D. Kiel, Reiner Kolla, Paul Molitor, Hans-Georg Osthof, Gisela Pitsch, Uwe Sparmann:
A graphical system for hierarchical specifications and checkups of VLSI circuits. 174-179 - Jung-Gen Wu:
Automatic knowledge acquisition in a digital circuit design system. 180-184
Compaction and circuit packing
- Yang Cai, D. F. Wong:
Optimal via-shifting in channel compaction. 186-190 - Chong-Min Kyung, Josef Widder, Dieter A. Mlynski:
Adaptive Cluster Growth (ACG): a new algorithm for circuit packing in rectilinear region. 191-195 - Shao-Jun Wei, Jacques Leroy, Raymond Crappe:
An efficient two-dimensional compaction algorithm for VLSI symbolic layout. 196-200 - Tomás Pérez Segovia, Anne-Françoise Joanblanq:
CACTUS: a symbolic CMOS two-dimensional compactor. 201-205
Combinational logic design optimization
- M. Pipponzi, Fabio Somenzi:
An iterative algorithm for the binate covering problem. 208-211 - Frédéric Mailhot, Giovanni De Micheli:
Technology mapping using boolean matching and don't care sets. 212-216 - Michel R. C. M. Berkelaar, Jochen A. G. Jess:
Gate sizing in MOS digital circuits with linear programming. 217-221 - Liliana Díaz-Olavarrieta, Safwat G. Zaky:
A new synthesis technique for multilevel combinational circuits. 222-227
Simulation I
- D. Patrick, Colin Lyden:
An event-driven transient simulation algorithm for MOS and bipolar circuits. 230-234 - M. T. van Stiphout, Jos T. J. van Eijndhoven, H. W. Buurman:
PLATO: a new piecewise linear simulation tool. 235-239 - Robert A. Cottrell:
Event-driven behavioural simulation of analogue transfer functions. 240-243 - Patrick Odent, Luc J. M. Claesen, Hugo De Man:
A combined waveform relaxation: waveform relaxation newton algorithm for efficient parallel circuit simulation. 244-248
Floorplanning
- Christian Masson, Denis Barbier, Remy Escassut, Daniel Winer, Gregory Chevallier, Pierre François Zeegers:
CHEOPS: an integrated VLSI floor planning and chip assembly system implemented in object oriented LISP. 250-256 - Noritake Yonezawa, Nobuyuki Nishiguchi, Atsushi Etani, Fumiaki Tsukuda, Ryuichi Hashishita:
A VLSI floorplanner based on "balloon" expansion. 257-261 - Kevin McCullen, John Thorvaldson, David Demaris, Patrick Lampin:
A system for floorplanning with hierarchical placement and wiring. 262-265 - Grazia Arato, Giuseppe Bussolino, Anna M. Fiammengo, Roberto Manione:
ACCORDO: second generation floor planning. 266-270
High level synthesis systems
- Dirk Lanneer, Francky Catthoor, Gert Goossens, Marc Pauwels, Jef L. van Meerbergen, Hugo De Man:
Open-ended system for high-level synthesis of flexible signal processors. 272-276 - Heinrich Krämer, Wolfgang Rosenstiel:
System synthesis using behavioural descriptions. 277-282 - Abdelhakim Safir, Bertrand Y. Zavidovique:
Towards a global solution to high level synthesis problems. 283-288
Simulation II
- Daniel K. Beece, Robert F. Damiano, Georgina Papp, R. Schoen:
The EVE companion simulator. 290-295 - Keith R. Dimond, Samir Hassan:
An incremental functional simulator implemented on a network of transputers. 296-300 - David T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham:
Derivation of signal flow for switch-level simulation. 301-305 - Jos T. J. van Eijndhoven, M. T. van Stiphout, H. W. Buurman:
Multirate integration in a direct simulation method. 306-311
Placement
- H. J. Kappen, F. M. J. de Bont:
An efficient placement method for large standard-cell and sea-of-gates designs. 312-316 - Jörn Garbers, Bernhard Korte, Hans Jürgen Prömel, E. Schwietzke, Angelika Steger:
VLSI: placement based on routing and timing information. 317-321 - Lukas P. P. P. van Ginneken, Ralph H. J. M. Otten:
Optimal slicing of plane point placements. 322-326 - Frank H. Huentemann, Utz G. Baitinger:
A gate-matrix oriented partitioning approach for multilevel logical networks. 327-331
Delay and CMOS testing
- Ankan K. Pramanick, Sudhakar M. Reddy:
On the fault coverage of delay fault detecting tests. 334-338 - Rene David, S. Rahal, J. L. Rainard:
Some relationships between delay testing and stuck-open testing in CMOS circuits. 339-343 - F. Darlay, Bernard Courtois:
Robust tests for stuck-open faults and design for testability of reconvergent fan-out CMOS logic networks. 344-349 - Niraj K. Jha, Qiao Tong:
Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring. 350-354
Databases and datastructuring
- Saleem M. Haider, Peng H. Ang:
A data-structuring technique for gridded VLSI layouts. 356-362 - Mattie N. Sim, Patrick M. Dewilde:
An object-oriented persistent database interface for CAD. 363-367 - Petra Drescher, Julia Miller, Gerhard Schulz:
Design management within a design environment. 368-373 - Mikael R. K. Patel:
A design representation for high level synthesis. 374-379
Physical verification and simulation
- Wolfgang Meier:
Hierarchical layout verification for submicron designs. 382-386 - Carlo Marazzini, Mauro Santomauro, Michele Taliercio:
CIRCE: a program for parasitic parameter extraction. 387-390 - Magdy S. Abadir, Jack Ferguson:
An improved layout verification algorithm (LAVA). 391-395 - Rolf Ernst, S. Sutarwala, J.-Y. Jou, M. Tong:
Simulation based verification of register-transfer level behavioral synthesis tools. 396-400
Low-level fault modelling and test generation
- Carles Ferrer, Joan Oliver, Elena Valderrama:
A new switch-level test pattern generation algorithm based on single path over a graph representation. 402-406 - Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch:
Fault modelling and fault equivalence in CMOS technology. 407-412 - João Paulo Teixeira, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves, R. Crespo:
A strategy for testability enhancement at layout level. 413-417 - Torsten Grüning, Udo Mahlstedt, Wilfried Daehn, Cengiz Özcan:
Accelerated test pattern generation by cone-oriented circuit partitioning. 418-421
Selected topics in CAD systems
- Eric William Burger, Guido Dedene:
Economics of point accelleration. 424-428 - F. Theeuwen:
Logic optimization on a concurrent processing computer. 429-433 - D. F. Burrows:
The use of computer-aided software engineering technology in systems and software design. 434-438 - Richard I. Hartley, Kenneth Welles II, Michael J. Hartman, Paul Delano, Abhijit Chatterjee:
Rapid prototyping using high density interconnects. 439-443
Routing
- Arvind Srinivasan, Ernest S. Kuh:
MOLE: a sea-of-gates detailed router. 446-450 - Bryan Preas:
Channel routing with non-terminal doglegs. 451-458 - Jason Cong, C. L. Liu:
On the k-layer planar subset and via minimization problems. 459-463 - Chang-Sheng Ying, Joshua Sook-Leung Wong, X. L. Hong, E. Q. Wang:
Path search on rectangular floorplan. 464-468
Test pattern generation and fault simulation
- Paolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda:
Diagnosis oriented test pattern generation. 470-474 - Wu-Tung Cheng, Janak H. Patel:
PROOFS: a super fast fault simulator for sequential circuits. 475-479 - Kaushik Roy, Jacob A. Abraham:
High level test generation using data flow descriptions. 480-484 - Christian Jay:
Experience in functional-level test generation and fault coverage in a silicon compiler. 485-490
Procedural interfaces
- J. P. Schupp, Johan Cockx, Luc J. M. Claesen, Hugo De Man:
SPI: an open interface integrating highly interactive electronic CAD tools. 492-495 - T. C. O. Young, Hilary J. Kahn:
A procedural interface to CAD data based on EDIF. 496-500 - Pedro Reis dos Santos, Helena Sarmento, Luís M. Vidigal:
Ghost/Spook: user interface and process management in the PACE framework. 501-505 - Bruno Poterie:
Storage mechanism for VHDL intermediate form. 506-510
Timing analysis and verification
- Hans Eveking, Christoph Mai:
Formal verification of timing conditions. 512-517 - P. Johannes, P. Das, Luc J. M. Claesen, Hugo De Man:
SLOCOP-II: a versatile timing verification system for MOSVLSI. 518-523 - Robert Tjärnström:
Automatic generation of timing specifications for CMOS transistor subnetworks. 524-528 - Denis Deschacht, P. Pinede, Michel Robert, Daniel Auvergne:
Path runner: an accurate and fast timing analyser. 529-533
Finit state machine synthesis I
- Lech Józwiak:
Efficent suboptimal state assignment for large sequential machines. 536-541 - Gabriele Saucier, Pascal Sicard, Laurent Bouchet:
Multi-level synthesis on PALs. 542-546 - Gabriele Saucier, Christopher Duff, Franck Poirot:
State assignment of controllers for optimal area implementation. 547-551 - Maria J. Avedillo, José M. Quintana, José Luis Huertas:
A new method for the state reduction of incompletely specified finite sequential machines. 552-556
Simulation modelling
- Veronika Eisele, Bernhard Hoppe, Oliver Kiehl:
Transmission gate delay models for circuit optimization. 558-562 - Thomas H. Krodel, Kurt Antreich:
An accurate model for ambiguity delay simulation. 563-567 - H. Warmers, D. Sass, Ernst-Helmut Horneber:
Switch-level timing models in the MOS simulator BRASIL. 568-572 - Norman F. Kelly, Holly E. Stump:
Software architecture of universal hardware modeler. 573-577 - Gordon F. Taylor:
Design to test migration: a tester and a simulator. 578-582
Physical design optimization
- Xianjin Yao, C. L. Liu:
Solution of a module orientation and rotation problem. 584-588 - Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski:
A new algorithm for transistor sizing in CMOS circuits. 589-593 - Uwe Hinsberger, Reiner Kolla:
Cell based performance optimization of combinational circuits. 594-599 - Reiner Kolla:
A dynamic programming approach to the power supply net sizing problem. 600-604 - Philippe Bondono, Ahmed Amine Jerraya, Armand Hornik, Bernard Courtois, D. Bonifas:
NAUTILE: a safe environment for silicon compilation. 605-609
Finite state machine synthesis - II
- Vishwani D. Agrawal, Kwang-Ting Cheng:
An architecture for synthesis of testable finite state machines. 612-616 - J. Zegers, Paul Six, Jan M. Rabaey, Hugo De Man:
CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler. 617-621 - Siegfried I. Mensch, Hans Martin Lipp:
Fuzzy specification of finite state machines. 622-626
Verification and PLA testing
- Peter C. Maxwell, Hans-Joachim Wunderlich:
The effectiveness of different test sets for PLAs. 628-632 - Che W. Chiou, Ted C. Yang:
Fully testable PLA design with minimal extra input. 633-638 - Eleanor Wu, Paul W. Rutkowski:
PEST: a tool for implementing pseudo-exhaustive self test. 639-643 - Andrzej Krasniewski:
Design for verification testability. 644-648
Novel approaches in placement
- Daniele D. Caviglia, Giacomo M. Bisio, Francesco Curatelli, L. Giovannacci, Luigi Raffo:
Pre-placement of VLSI blocks through learning neural networks. 650-654 - M. Razaz, J. Gan:
Fuzzy set based initial placement for IC layout. 655-659 - Khushro Shahookar, Pinaki Mazumder:
GASP: a Genetic Algorithm for Standard cell Placement. 660-664 - M. Y. Yu, Xiaoyan Hong, Y. E. Lien, Z. Z. Ma, J. G. Bo, W. J. Zhuang:
A new clustering approach and its application to BBL placement. 665-669
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