18. FCCM 2010: Charlotte, North Carolina, USA

Computer Vision and Graphics Processing

• Dimitris Bouris, Antonis Nikitakis, Ioannis Papaefstathiou:
  Fast and Efficient FPGA-Based Feature Detection Employing the SURF Algorithm. 3-10
  
• Daniel Hefenbrock, Jason Oberg, Nhat Thanh, Ryan Kastner, Scott B. Baden:
  Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs. 11-18
  
• Srinidhi Kestur, Sungho Park, Kevin M. Irick, Vijaykrishnan Narayanan:
  Accelerating the Nonuniform Fast Fourier Transform Using FPGAs. 19-26
  

Short Papers

• Junguk Cho, Bridget Benson, Sunsern Cheamanunkul, Ryan Kastner:
  Increased Performace of FPGA-Based Color Classification System. 29-32
  
• Seunghun Jin, Dongkyun Kim, Duc Dung Nguyen, Jae Wook Jeon:
  Pipelined Hardware Architecture for High-Speed Optical Flow Estimation Using FPGA. 33-36
  

Run-Time Systems

• Jason Agron, David L. Andrews:
  Distributed Hardware-Based Microkernels: Making Heterogeneous OS Functionality a System Primitive. 39-46
  
• Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
  Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration. 47-54
  
• Tobias Becker, Wayne Luk, Peter Y. K. Cheung:
  Energy-Aware Optimisation for Run-Time Reconfiguration. 55-62
  

Short Papers

• Yi Lu, Thomas Marconi, Koen Bertels, Georgi Gaydadjiev:
  A Communication Aware Online Task Scheduling Algorithm for FPGA-Based Partially Reconfigurable Systems. 65-68
  
• Dirk Koch, Christian Beckhoff, Jim Tørresen:
  Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs. 69-72
  
• Anargyros Ilias, Kyprianos Papadimitriou, Apostolos Dollas:
  Combining Duplication, Partial Reconfiguration and Software for On-line Error Diagnosis and Recovery in SRAM-Based FPGAs. 73-76
  

Supercomputing

• Tomás Martínek, Matej Lexa:
  Hardware Acceleration of Approximate Tandem Repeat Detection. 79-86
  
• Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain:
  Rapid RNA Folding: Analysis and Acceleration of the Zuker Recurrence. 87-94
  
• Miaoqing Huang, Özlem Kilic:
  Reaping the Processing Potential of FPGA on Double-Precision Floating-Point Operations: An Eigenvalue Solver Case Study. 95-102
  

Short Papers

• Tarek Ould Bachir, Jean-Pierre David:
  Performing Floating-Point Accumulation on a Modern FPGA in Single and Double Precision. 105-108
  
• Guiming Wu, Yong Dou, Gregory D. Peterson:
  Blocking LU Decomposition for FPGAs. 109-112
  
• F. Javier Garrigós, J. Javier Martínez, Isidro Villo, F. Javier Toledo, José Manuel Ferrández:
  Acceleration of a DWT-Based Algorithm for Short Exposure Stellar Images Processing on a HPRC Platform. 113-116
  

Open-Source Tools and Platforms

• Gonzalo Carvajal, Sebastian Fischmeister:
  A TDMA Ethernet Switch for Dynamic Real-Time Communication. 119-126
  
• Jason R. Villarreal, Adrian Park, Walid A. Najjar, Robert Halstead:
  Designing Modular Hardware Accelerators in C with ROCCC 2.0. 127-134
  
• Ken Eguro:
  SIRC: An Extensible Reconfigurable Computing Communication API. 135-138
  

Application Development and CAD Tools

• Christopher E. Neely, Gordon J. Brebner, Weijia Shang:
  ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs. 141-148
  
• Peter Jamieson, Kenneth B. Kent, Farnaz Gharibian, Lesley Shannon:
  Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research. 149-156
  
• David Boland, George A. Constantinides:
  Automated Precision Analysis: A Polynomial Algebraic Approach. 157-164
  

Short Papers

• Barry Bond, Kerry Hammil, Lubomir Litchev, Satnam Singh:
  FPGA Circuit Synthesis of Accelerator Data-Parallel Programs. 167-170
  
• Jimmy Xu, Nikhil Subramanian, Adam Alessio, Scott Hauck:
  Impulse C vs. VHDL for Accelerating Tomographic Reconstruction. 171-174
  
• Andrew W. H. House, Manuel Saldaña, Paul Chow:
  Integrating High-Level Synthesis into MPI. 175-178
  
• Joon Edward Sim, Weng-Fai Wong, Gregor Walla, Tobias Ziermann, Jürgen Teich:
  Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems. 179-182
  

Machine Learning, String Matching, and Networking

• Faisal Khan, Nicholas Hosein, Scott Vernon, Soheil Ghiasi:
  BURAQ: A Dynamically Reconfigurable System for Stateful Measurement of Network Traffic. 185-192
  
• Hoang Le, Viktor K. Prasanna:
  A Memory-Efficient and Modular Approach for String Matching on FPGAs. 193-200
  
• Sang Kyun Kim, Peter Leonard McMahon, Kunle Olukotun:
  A Large-Scale Architecture for Restricted Boltzmann Machines. 201-208
  

Short Papers

• Markos Papadonikolakis, Christos-Savvas Bouganis:
  A Heterogeneous FPGA Architecture for Support Vector Machine Training. 211-214
  
• Yeim-Kuan Chang, Yi-Shang Lin, Cheng-Chien Su:
  A High-Speed and Memory Efficient Pipeline Architecture for Packet Classification. 215-218
  

Systems and Architectures

• Tayo Oguntebi, Sungpack Hong, Jared Casper, Nathan Grasso Bronson, Christos Kozyrakis, Kunle Olukotun:
  FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures. 221-228
  
• Hadi Parandeh-Afshar, Paolo Ienne:
  Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance. 229-236
  
• Daniel Ziener, Florian Baueregger, Jürgen Teich:
  Using the Power Side Channel of FPGAs for Communication. 237-244
  

Short Papers

• Bernd Scheuermann:
  Design of a Reconfigurable Hybrid Database System. 247-250
  
• Jason Cong, Yi Zou:
  A Comparative Study on the Architecture Templates for Dynamic Nested Loops. 251-254
  
• Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides:
  A Scripting Engine for Combining Design Transformations. 255-258
  
• Diana Göhringer, Michael Hübner, Michael Benz, Jürgen Becker:
  A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip. 259-262
  

Encryption

• J. L. Shafer, S. W. Schneider, J. T. Butler, P. Stanica:
  Enumeration of Bent Boolean Functions by Reconfigurable Computer. 265-272
  
• Jens-Peter Kaps, Rajesh Velegalati:
  DPA Resistant AES on FPGA Using Partial DDL. 273-280
  

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