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ORCID15. FPGA 2007: Monterey, CA, USA
- André DeHon, Mike Hutton:
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007. ACM 2007, ISBN 978-1-59593-600-4
Architecture and technology
- Mingjie Lin, Abbas El Gamal:
A routing fabric for monolithically stacked 3D-FPGA. 3-12 - Scott C. Smith:
Design of a logic element for implementing an asynchronous FPGA. 13-22 - Wenyi Feng, Sinan Kaptanoglu:
Designing efficient input interconnect blocks for LUT clusters using counting and entropy. 23-32 - Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong
, Wayne Luk, Bradley R. Quinton:
A synthesizable datapath-oriented embedded FPGA fabric. 33-41
Implementation and emulation
- David Slogsnat, Alexander Giese, Ulrich Brüning:
A versatile, low latency HyperTransport core. 45-52 - Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh:
An FPGA-based Pentium in a complete desktop system. 53-59 - Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen:
A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA. 60-68
CAD
- Satish Sivaswamy, Kia Bazargan:
Variation-aware routing for FPGAs. 71-79 - Yan Lin, Lei He:
Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation. 80-88 - Kai Zhu:
Post-route LUT output polarity selection for timing optimization. 89-96
FPGA-based computing
- Jason Cong, Guoling Han, Wei Jiang:
Synthesis of an application-specific soft multiprocessor system. 99-107 - Bita Gorjiara, Daniel Gajski:
FPGA-friendly code compression for horizontal microcoded custom IPs. 108-115 - Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun:
A practical FPGA-based framework for novel CMP research. 116-125
Panel
- Michael J. Wirthlin, Misha Burich, Andrew Guyler, Brian Von Herzen:
High-level languages: the future or a passing fad? 127
Integrating FPGAs in high-performance computing
- Paul Chow, Mike Hutton:
Integrating FPGAs in high-performance computing: introduction. 131 - Nathan Woods:
Integrating FPGAs in high-performance computing: the architecture and implementation perspective. 132 - Satnam Singh:
Integrating FPGAs in high-performance computing: programming models for parallel systems -- the programmer's perspective. 133-135
CAD and architecture
- Jason Cong, Kirill Minkovich:
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs. 139-147 - Kevin Oo Tinmaung, David Howland, Russell Tessier:
Power-aware FPGA logic synthesis using binary decision diagrams. 148-155 - Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton:
GlitchLess: an active glitch minimization technique for FPGAs. 156-165
Variation and yield
- Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. 169-177 - N. Pete Sedcole, Peter Y. K. Cheung:
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. 178-187 - Dirk Koch, Christian Haubelt, Jürgen Teich:
Efficient hardware checkpointing: concepts, overhead analysis, and implementation. 188-196
Security
- Nicholas Weaver, Vern Paxson, José M. González:
The shunt: an FPGA-based accelerator for network intrusion prevention. 199-206 - Tim Güneysu, Christof Paar, Jan Pelzl:
Attacking elliptic curve cryptosystems with special-purpose hardware. 207-215 - Nathan Jachimiec, Fernando Martinez-Vallina, Jafar Saniie:
CReconfigurable finite field instruction set architecture. 216-220
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