19. FPGA 2012: Monterey, CA, USA

Applications I

• Anh-Tuan Hoang, Takeshi Fujino:
  Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA. 1-10
  
• Chih-Hsun Chou, Fong Pong, Nian-Feng Tzeng:
  Speedy FPGA-based packet classifiers with low on-chip memory requirements. 11-20
  
• Minxi Jin, Tsutomu Maruyama:
  A real-time stereo vision system using a tree-structured dynamic programming on FPGA. 21-24
  
• Scott Bailie, Miriam Leeser:
  Incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation. 25-28
  
• Matthias Hinkfoth, Enrico Heinrich, Sebastian Vorköper, Volker Kühn, Ralf Salomon:
  X-ORCA: FPGA-based wireless localization in the sub-millimeter range. 29-32
  
• John Curreri, Greg Stitt, Alan D. George:
  Communication visualization for bottleneck detection of high-level synthesis applications. 33-36
  

Design studies

• Michael Papamichael, James C. Hoe:
  CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs. 37-46
  
• Jeremy Fowers, Greg Brown, Patrick Cooke, Greg Stitt:
  A performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applications. 47-56
  
• Gary Chun Tak Chow, Anson Hong Tak Tse, Qiwei Jin, Wayne Luk, Philip Heng Wai Leong, David B. Thomas:
  A mixed precision Monte Carlo methodology for reconfigurable accelerator systems. 57-66
  
• Zefu Dai, Jianwen Zhu:
  Saturating the transceiver bandwidth: switch fabric design on FPGAs. 67-76
  

CAD

• Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson:
  The VTR project: architecture and CAD for FPGAs from verilog to routing. 77-86
  
• Maysam Lavasani, Larry Dennison, Derek Chiou:
  Compiling high throughput network processors. 87-96
  
• Nikil Mehta, Raphael Rubin, André DeHon:
  Limit study of energy & delay benefits of component-specific routing. 97-106
  
• Warren Wai-Kit Shum, Jason Helge Anderson:
  Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power. 107-110
  
• Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Dean Brown, Tomasz S. Czajkowski:
  Impact of FPGA architecture on resource sharing in high-level synthesis. 111-114
  
• Qinghong Wu, Kenneth S. McElvain:
  A fast discrete placement algorithm for FPGAs. 115-118
  

Architecture I

• Hadi Parandeh-Afshar, Hind Benbihi, David Novo, Paolo Ienne:
  Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones. 119-128
  
• Jason Xin Zheng, Miodrag Potkonjak:
  Securing netlist-level FPGA design through exploiting process variation and degradation. 129-138
  
• Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe, Ken Mai:
  Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing. 139-142
  

Applications II

• Wendi Wang, Bo Duan, Wen Tang, Chunming Zhang, Guangming Tan, Peiheng Zhang, Ninghui Sun:
  A coarse-grained stream architecture for cryo-electron microscopy images 3D reconstruction. 143-152
  
• Sameh W. Asaad, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin D. Parker, Thomas Roewer, Proshanta Saha, Todd Takken, José A. Tierno:
  A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. 153-162
  
• Jianwen Chen, Jason Cong, Ming Yan, Yi Zou:
  FPGA-accelerated 3D reconstruction using compressive sensing. 163-166
  
• Haoran Li, Youn Sung Park, Zhengya Zhang:
  Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation. 167-170
  
• Nathaniel H. Rollins, Michael J. Wirthlin:
  Reliability of a softcore processor in a commercial SRAM-based FPGA. 171-174
  

Tools and abstractions

• Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer:
  Leveraging latency-insensitivity to ease multiple FPGA design. 175-184
  
• David Boland, George A. Constantinides:
  A scalable approach for automated precision analysis. 185-194
  
• Samuel Bayliss, George A. Constantinides:
  Optimizing SDRAM bandwidth for custom FPGA loop accelerators. 195-204
  
• Robert Kirchgessner, Greg Stitt, Alan D. George, Herman Lam:
  VirtualRC: a virtual FPGA platform for applications and tools portability. 205-208
  

Compute engines and run-time systems

• Charles Eric LaForest, Ming G. Liu, Emma Rae Rapati, J. Gregory Steffan:
  Multi-ported memories for FPGAs via XOR. 209-218
  
• Charles Eric LaForest, John Gregory Steffan:
  OCTAVO: an FPGA-centric processor family. 219-228
  
• Zhiduo Liu, Aaron Severance, Satnam Singh, Guy G. F. Lemieux:
  Accelerator compiler for the VENICE vector processor. 229-232
  
• Vincent Mirian, Paul Chow:
  FCache: a system for cache coherent processing on FPGAs. 233-236
  
• Hui Yan Cheah, Suhaib A. Fahmy, Douglas L. Maskell, Chidamber Kulkarni:
  A lean FPGA soft processor built using a DSP block. 237-240
  
• Lingkan Gong, Oliver Diessel:
  Functionally verifying state saving and restoration in dynamically reconfigurable systems. 241-244
  

Architecture II

• Assem A. M. Bsoul, Steven J. E. Wilton:
  A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs. 245-254
  
• Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk:
  Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. 255-264
  

Poster session 1

• Yupeng Chen, Bertil Schmidt, Douglas L. Maskell:
  Accelerating short read mapping on an FPGA (abstract only). 265
  
• Mei Wen, Nan Wu, Qianming Yang, Chunyuan Zhang, Liang Zhao:
  The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable FPGAs (abstract only). 265
  
• Fatemeh Sadat Pourhashemi, Morteza Saheb Zamani:
  Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only). 265
  
• Declan Walsh, Piotr Dudek:
  A field programmable array core for image processing (abstract only). 266
  
• Sundaram Ananthanarayanan, Chirag Ravishankar, Siddharth Garg, Andrew A. Kennings:
  EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only). 266
  

Poster session 2

• Jesus Savage, Rodrigo Savage, Marco Morales-Aguirre, Ángel Fernando Kuri Morales:
  Adaptive FPGA-based robotics state machine architecture derived with genetic algorithms (abstract only). 267
  
• Yong Fu, Chi Wang, Liguang Chen, Jinmei Lai:
  A novel full coverage test method for CLBs in FPGA (abstract only). 267
  
• André Seffrin, Sorin A. Huss:
  Constraint-driven automatic generation of interconnect for partially reconfigurable architectures (abstract only). 267
  
• Juinn-Dar Huang, Ya-Shih Huang, Mi-Yu Hsu, Han-Yuan Chang:
  Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only). 268
  
• Wei Ting Loke, Yajun Ha:
  Power-aware FPGA technology mapping for programmable-VT architectures (abstract only). 268
  
• Jason Cong, Bingjun Xiao:
  FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only). 268
  

Poster session 3

• Proshanta Saha, Chuck Haymes, Ralph Bellofatto, Bernard Brezzo, Mohit Kapur, Sameh W. Asaad:
  Efficient in-system RTL verification and debugging using FPGAs (abstract only). 269
  
• Chris C. Wang, Guy G. F. Lemieux:
  Parallel FPGA placement based on individual LUT placement (abstract only). 269
  
• Robin Panda, Scott Hauck:
  Dataflow-driven execution control in a coarse-grained reconfigurable array (abstract only). 269
  
• S. Alexander Chin, Paul Chow:
  OpenCL memory infrastructure for FPGAs (abstract only). 269-270
  
• Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So:
  Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only). 270
  

Poster session 4

• Masahiro Fujita, Hiroaki Yoshida:
  Post-silicon debugging targeting electrical errors with patchable controllers (abstract only). 271
  
• Berkin Akin, Peter A. Milder, Franz Franchetti, James C. Hoe:
  Algorithm and architecture optimization for large size two dimensional discrete fourier transform (abstract only). 271
  
• Hugo A. Andrade, Arkadeb Ghosal, Rhishikesh Limaye, Sadia Malik, Newton Petersen, Kaushik Ravindran, Trung N. Tran, Guoqiang Wang, Guang Yang:
  Early timing estimation for system-level design using FPGAs (abstract only). 271
  
• Yi-Hua E. Yang, Oguzhan Erdem, Viktor K. Prasanna:
  Scalable architecture for 135 GBPS IPv6 lookup on FPGA (abstract only). 272
  

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