12. FPL 2002: Montpellier, France

Keynote Address

• Paul Master:
  The Age of Adaptive Computing Is Here. 1-3
  

Trends

• Reiner W. Hartenstein:
  Disruptive Trends by Data-Stream-Based Computing. 4
  
• Gordon J. Brebner:
  Multithreading for Logic-Centric Systems. 5-14
  

Rapid Prototyping

• Siavash Bayat Sarmadi, Seyed Ghassem Miremadi, Ghazanfar Asadi, Ali Reza Ejlali:
  Fast Prototyping with Co-operation of Simulation and Emulation. 15-25
  
• Helena Krupnova, Veronique Meurou, Christophe Barnichon, Carlos Serra, Farid Morsi:
  How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project. 26-35
  

FPGA Synthesis

• Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland:
  Implementing Asynchronous Circuits on LUT Based FPGAs. 36-46
  
• Beniamino Di Martino, Nicola Mazzocca, Giacinto Paolo Saggese, Antonio G. M. Strollo:
  A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations. 47-58
  

Custom Computing Engines

• Katherine Compton, Akshay Sharma, Shawn Phillips, Scott Hauck:
  Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems. 59-68
  
• Jawad Khan, Manish Handa, Ranga Vemuri:
  iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications. 69-78
  
• Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers:
  Field-Programmable Custom Computing Machines - A Taxonomy -. 79-88
  

DSP Applications 1

• Katarzyna Leijten-Nowak, Jef L. van Meerbergen:
  Embedded Reconfigurable Logic Core for DSP Applications. 89-101
  
• Francisco Cardells-Tormo, Javier Valls-Coquillat, Vicenc Almenar-Terre, Vicente Torres-Carot:
  Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard. 102-111
  
• Chris Dick, Fred Harris:
  FPGA QAM Demodulator Design. 112-121
  

Reconfigurable Fabrics

• Guy G. Lemieux, David M. Lewis:
  Analytical Framework for Switch Block Design. 122-131
  
• Aneesh Koorapaty, Lawrence T. Pileggi:
  Modular, Fabric-Specific Synthesis for Programmable Architectures. 132-141
  
• Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung:
  On Optimum Designs of Universal Switch Blocks. 142-151
  

Dynamic Reconfiguration 1

• Ian Robertson, James Irvine, Patrick Lysaght, David Robinson:
  Improved Functional Simulation of Dynamically Reconfigurable Logic. 152-161
  
• Sergio López-Buedo, Paula Riviere, Pablo Pernas, Eduardo I. Boemo:
  Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology. 162-170
  
• Gerard J. M. Smit, Paul J. M. Havinga, Lodewijk T. Smit, Paul M. Heysters, Michèl A. J. Rosien:
  Dynamic Reconfiguration in Mobile Systems. 171-181
  
• Edson L. Horta, John W. Lockwood, Sergio Takeo Kofuji:
  Using PARBIT to Implement Partial Run-Time Reconfigurable Systems. 182-191
  

DSP Applications 2

• Richard H. Turner, Roger Woods, Tim Courtney:
  Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs. 192-201
  
• Stephen J. Melnikoff, Steven F. Quigley, Martin J. Russell:
  Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models. 202-211
  
• Antony Jamin, Petri Mähönen:
  FPGA Implementation of the Wavelet Packet Transform for High Speed Communications. 212-221
  
• Alex Carreira, Trevor W. Fox, Laurence E. Turner:
  A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBits^TM. 222-231
  

Routing & Placement

• Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic:
  Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. 232-241
  
• PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
  Rapid and Reliable Routability Estimation for FPGAs. 242-252
  
• Martin Danek, Zdenek Muzikár:
  Integrated Iterative Approach to FPGA Placement. 253-262
  
• Lucídio dos Anjos Formiga Cabral, Júlio S. Aude, Nelson Maculan:
  TDR: A Distributed-Memory Parallel Routing Algorithm for FPGAs. 263-270
  

Dynamic Reconfiguration 2

• Rafal Kielbik, Juan Manuel Moreno, Andrzej Napieralski, Grzegorz Jablonski, Tomasz Szymanski:
  High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices. 271-280
  
• Yoshiki Yamaguchi, Yosuke Miyajima, Tsutomu Maruyama, Akihiko Konagaya:
  High Speed Homology Search Using Run-Time Reconfiguration. 281-291
  
• Matthias Dyer, Christian Plessl, Marco Platzner:
  Partially Reconfigurable Cores for Xilinx Virtex. 292-301
  
• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. M. Ferreira:
  On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs. 302-311
  

Power Estimation

• Kara K. W. Poon, Andy Yan, Steven J. E. Wilton:
  A Flexible Power Model for FPGAs. 312-321
  
• Oswaldo Cadenas, Graham M. Megson:
  A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs. 322-331
  
• Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni:
  Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. 332-339
  
• Elias Todorovich, M. Gilabert, Gustavo Sutter, Sergio López-Buedo, Eduardo I. Boemo:
  A Tool for Activity Estimation in FPGAs. 340-349
  

Synthesis Issues

• Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo:
  FSM Decomposition for Low Power in FPGA. 350-359
  
• Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
  Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. 360-369
  
• Khaled Benkrid, Danny Crookes, Abdsamad Benkrid, S. Belkacemi:
  A Prolog-Based Hardware Development Environment. 370-380
  
• Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner:
  Fly - A Modifiable Hardware Compiler. 381-390
  

Keynote Address

• Ivo Bolsens:
  Challenges and Opportunities for FPGA Platforms. 391-392
  

Communication Applications 1

• Masayuki Kirimura, Yoshifumi Takamoto, Takanori Mori, Keiichi Yasumoto, Akio Nakata, Teruo Higashino:
  Design and Implementation of FPGA Circuits for High Speed Network Monitors. 393-403
  
• Maya Gokhale, Dave Dubois, Andy Dubois, Mike Boorman, Steve Poole, Vic Hogsett:
  Granidt: Towards Gigabit Rate Network Intrusion Detection Technology. 404-413
  

New Technologies

• Channakeshav, Kuan Zhou, Jong-Ru Guo, Chao You, Bryan S. Goda, Russell P. Kraft, John F. McDonald:
  Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques. 414-423
  
• Tyson S. Hall, Paul E. Hasler, David V. Anderson:
  Field-Programmable Analog Arrays: A Floating-Gate Approach. 424-433
  

Reconfigurable Architectures

• Kazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi Yoshida:
  A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model. 434-443
  
• Thilo Pionteck, Peter Zipf, Lukusa D. Kabulepa, Manfred Glesner:
  A Framework for Teaching (Re)Configurable Architectures in Student Projects. 444-451
  

Communication Applications 2

• Young H. Cho, Shiva Navab, William H. Mangione-Smith:
  Specialized Hardware for Deep Network Packet Filtering. 452-461
  
• Thomas Buerner:
  Implementation of a Successive Erasure BCH(16, 7, 6) Decoder and Performance Simulation by Rapid Prototyping. 462-471
  
• Javier Ramírez, Antonio García:
  U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation. 472-481
  

Multimedia Applications

• Simon D. Haynes, Henry G. Epsom, Richard J. Cooper, Paul L. McAlpine:
  UltraSONIC: A Reconfigurable Architecture for Video Image Processing. 482-491
  
• Trevor W. Fox, Laurence E. Turner:
  Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA. 492-502
  
• Alexander Staller, Peter Dillinger, Reinhard Männer:
  Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA. 503-512
  

FPGA-based Arithmetic 1

• Jean-Luc Beuchat, Arnaud Tisserand:
  Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices. 513-522
  
• Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James Hwang:
  Automating Customisation of Floating-Point Designs. 523-533
  
• Ju-wook Jang, Seonil Choi, Viktor K. Prasanna:
  Energy-Efficient Matrix Multiplication on FPGAs. 534-544
  

Reconfigurable Processors

• Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung:
  Run-Time Adaptive Flexible Instruction Processors. 545-555
  
• José T. de Sousa, Fernando M. Gonçalves, Nuno Barreiro, João Moura:
  DARP - A Digital Audio Reconfigurable Processor. 556-566
  
• Stephen Charlwood, Jonathan Mangnall, Steven F. Quigley:
  System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors. 567-576
  
• Kurt K. Ting, Steve C. L. Yuen, Kin-Hong Lee, Philip Heng Wai Leong:
  An FPGA Based SHA-256 Processor. 577-585
  

Testing & Fault-Tolerance

• Peter Zipf, Manfred Glesner, Christine Bauer, Hans Wojtkowiak:
  Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension. 586-595
  
• Andrzej Krasniewski:
  On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs. 596-606
  
• Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
  Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs. 607-615
  
• Andrzej Krasniewski:
  Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs. 616-626
  

FPGA-based Arithmetic 2

• Rudolf Matousek, Milan Tichý, Zdenek Pohl, Jiri Kadlec, Christopher I. Softley, Nick Coleman:
  Logarithmic Number System and Floating-Point Arithmetics on FPGA. 627-636
  
• Eric Roesler, Brent E. Nelson:
  Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture. 637-646
  
• Silviu M. S. A. Chiricescu, Michael A. Schuette, Robin Glinton, Herman Schmit:
  Morphable Multipliers. 647-656
  
• Pavle Belanovic, Miriam Leeser:
  A Library of Parameterized Floating-Point Modules and Their Use. 657-666
  

Reconfigurable Systems

• Tony Stansfield:
  Wordlength as an Architectural Parameter for Reconfigurable Computing Devices. 667-676
  
• Massimo Baleani, Massimo Conti, Alberto Ferrari, Valerio Frascolla, Alberto L. Sangiovanni-Vincentelli:
  An Enhanced POLIS Framework for Fast Exploration and Implementation of I/O Subsystems on CSoC Platforms. 677-686
  
• Grant B. Wigley, David A. Kearney, David Warren:
  Introducing ReConfigME: An Operating System for Reconfigurable Computing. 687-697
  
• Reetinder P. S. Sidhu, Viktor K. Prasanna:
  Efficient Metacomputation Using Self-Reconfiguration. 698-709
  

Image Processing

• Miguel Arias-Estrada, Eduardo Rodríguez-Palacios:
  An FPGA Co-processor for Real-Time Visual Tracking. 710-719
  
• Viktor Fischer, Milos Drutarovský, Rastislav Lukac:
  Implementation of 3-D Adaptive LUM Smoother in Reconfigurable Hardware. 720-729
  
• Abbes Amira, Ahmed Bouridane, Peter Milligan, Faycal Bensaali:
  Custom Coprocessor Based Matrix Algorithms for Image and Signal Processing. 730-739
  
• Nazeeh Aranki, Alexander Moopenn, Raoul Tawel:
  Parallel FPGA Implementation of the Split and Merge Discrete Wavelet Transform. 740-749
  

Crypto Applications 1

• Tim Kerins, Emanuel M. Popovici, William P. Marnane, Patrick Fitzpatrick:
  Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2). 750-759
  
• Antti Hämäläinen, Matti Tommiska, Jorma Skyttä:
  8 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm. 760-769
  
• Emmanuel A. Moreira, Paul L. McAlpine, Simon D. Haynes:
  Rijndael Cryptographic Engine on the UltraSONIC Reconfigurable Platform. 770-779
  
• Jean-Jacques Quisquater, François-Xavier Standaert, Gaël Rouvroy, Jean-Pierre David, Jean-Didier Legat:
  A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation. 780-789
  

Keynote Address

• Rudy Lauwereins:
  Creating a World of Smart Re-configurable Devices. 790-794
  

Multitasking

• Théodore Marescaux, Andrei Bartic, Diederik Verkest, Serge Vernalde, Rudy Lauwereins:
  Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs. 795-805
  
• Wesley J. Landaker, Michael J. Wirthlin, Brad L. Hutchings:
  Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System. 806-815
  

Special Architectures

• Tuomas Valtonen, Jouni Isoaho, Hannu Tenhunen:
  The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance. 816-825
  
• Zbigniew Kokosinski, Wojciech Sikora:
  An FPGA Implementation of a Multi-comparand Multi-search Associative Processor. 826-835
  

Crypto Applications 2

• Anna Labbé, Annie Pérez:
  AES Implementation on FPGA: Time - Flexibility Tradeoff. 836-844
  
• François Koeune, Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Pierre David, Jean-Didier Legat:
  An FPGA Implementation of the Linear Cryptanalysis. 845-852
  

Compilation Techniques

• Mihai Budiu, Seth Copen Goldstein:
  Compiling Application-Specific Hardware. 853-863
  
• João M. P. Cardoso, Markus Weinhardt:
  XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture. 864-874
  
• Justin L. Tripp, Preston A. Jackson, Brad L. Hutchings:
  Sea Cucumber: A Synthesizing Compiler for FPGAs. 875-885
  

DSP Applications 3

• Joan Carletta, M. D. Rayman:
  Practical Considerations in the Synthesis of High Performance Digital Filters for Implementation on FPGAs. 886-896
  
• Uwe Meyer-Bäse, Javier Ramírez, Antonio García:
  Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs. 897-904
  
• Francisco Cardells-Tormo, Javier Valls-Coquillat:
  High Performance Quadrature Digital Mixers for FPGAs. 905-914
  

Complex Applications

• Oskar Mencer, Zhining Huang, Lorenz Huelsbergen:
  HAGAR: Efficient Multi-context Graph Processors. 915-924
  
• Benjamin Carrión Schäfer, Steven F. Quigley, Andrew H. C. Chan:
  Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform. 925-934
  
• Kai-Pui Lam, Sui-Tung Mak:
  On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach. 935-944
  

Architecture Implementation

• Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli:
  REFLIX: A Processor Core for Reactive Embedded Applications. 945-945
  
• Girish Venkataramani, Suraj Sudhir, Mihai Budiu, Seth Copen Goldstein:
  Factors Influencing the Performance of a CPU-RFU Hybrid Architecture. 955-965
  
• Alfredo Sanz, José I. García-Nicolás, Isidoro Urriza:
  Implementing Converters in FPLD. 966-975
  
• Domingo Benitez:
  A Quantitative Understanding of the Performance of Reconfigurable Coprocessors. 976-986
  

Design Flow

• Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier:
  Integration of Reconfigurable Hardware into System-Level Design. 987-996
  
• Frank Wolz, Reiner Kolla:
  A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures. 997-1006
  
• Ramaswamy Ramaswamy, Russell Tessier:
  The Integration of SystemC and Hardware-Assisted Verification. 1007-1016
  
• Alireza Kaviani:
  Using Design Hierarchy to Improve Quality of Results in FPGAs. 1017-1026
  

Miscellaneous

• George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis:
  Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. 1027-1036
  
• Naoto Kaneko, Hideharu Amano:
  A General Hardware Design Model for Multicontext FPGAs. 1037-1047
  
• Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert:
  Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations. 1048-1057
  
• Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
  A Compilation Framework for a Dynamically Reconfigurable Architecture. 1058-1067
  

Short Papers

• Shuichi Ichikawa, Shoji Yamamoto:
  Data Dependent Circuit for Subgraph Isomorphism Problem. 1068-1071
  
• Jan Schmidt, Martin Novotný, Martin Jäger, Milos Becvár, Michal Jáchim:
  Exploration of Design Space in ECDSA. 1072-1075
  
• Issam Damaj, Sohaib Majzoub, Hassan B. Diab:
  2D and 3D Computer Graphics Algorithms under MORPHOSYS. 1076-1079
  
• Spyros Blionas, Kostas Masselos, Chrissavgi Dre, Christos Drosos, F. Z. Ieromnimon, T. Pagonis, A. Pneymatikakis, Anna Tatsaki, T. Trimis, A. Vontzalidis, Dimitris Metafas:
  A HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-Chip. 1080-1083
  
• Stephanie McBader, Luca Clementel, Alvise Sartori, Andrea Boni, Peter Lee:
  SoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor. 1084-1087
  
• Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba:
  Real-Time Medical Diagnosis on a Multiple FPGA-based System. 1088-1091
  
• Kazuo Aoyama, Hiroshi Sawada:
  Threshold Element-Based Symmetric Function Generators and Their Functional Extension. 1092-1096
  
• Wolfgang Schlecker, Achim Engelhart, Werner G. Teich, Hans-Jörg Pfleiderer:
  Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks. 1097-1100
  
• James Hwang, Jonathan Ballagh:
  Building Custom FIR Filters Using System Generator. 1101-1104
  
• Klaus Feske, Georg Heinrich, Berndt Fritzsche, Mark Langer:
  SoC Based Low Cost Design of Digital Audio Broadcasting Transport Network Applications. 1105-1109
  
• Ernest Jamro, Kazimierz Wiatr:
  Dynamic Constant Coefficient Convolvers Implemented in FPGAs. 1110-1113
  
• Urs Kanus, Gregor Wetekam, Johannes Hirche, Michael Meißner:
  VIZARD II: An FPGA-based Interactive Volume Rendering System. 1114-1117
  
• Naoyuki Izu, Tomonori Yokoyama, Junichiro Tsuchiya, Konosuke Watanabe, Hideharu Amano:
  RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing. 1118-1121
  
• Filip Miletic, Rene van Leuken, Alexander de Graaf:
  General Purpose Prototyping Platform for Data-Processor Research and Development. 1122-1125
  
• Tomoyoshi Kobori, Tsutomu Maruyama:
  High Speed Computation of Three Dimensional Cellular Automata with FPGA. 1126-1130
  
• Sylvain Poussier, Hassan Rabah, Serge Weber:
  SOPC-based Embedded Smart Strain Gage Sensor. 1131-1134
  
• Yajun Ha, Radovan Hipik, Serge Vernalde, Diederik Verkest, Marc Engels, Rudy Lauwereins, Hugo De Man:
  Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications. 1135-1138
  
• Roberto Gaudino, Vito De Feo, Marcello Chiaberge, Claudio Sansoè:
  An FPGA-based Node Controller for a High Capacity WDM Optical Packet Network. 1139-1143
  
• Francis Calmon, M. Fathallah, P. J. Viverge, Christian Gontrand, Jordi Carrabina, P. Foussier:
  FPGA and Mixed FPGA-DSP Implementations of Electrical Drive Algorithms. 1144-1147
  
• Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk:
  Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer. 1148-1151
  
• Dylan Carline, Paul Coulton:
  A Novel Watermarking Technique for LUT Based FPGA Designs. 1152-1155
  
• Martin Henz, Edgar Tan, Roland H. C. Yap:
  Implementing CSAT Local Search on FPGAs. 1156-1159
  
• Adronis Niyonkuru, Göran Eggers, Hans Christoph Zeidler:
  A Reconfigurable Processor Architecture. 1160-1163
  
• Sebastian Friebe, Steffen Köhler, Rainer G. Spallek, Henrik Juhr, Klaus Künanz:
  A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor. 1164-1167
  
• Steve Guccione, Eric Keller:
  Gene Matching Using JBits. 1168-1171
  
• Daniel G. Saab, Fatih Kocan, Jacob A. Abraham:
  Massively Parallel/Reconfigurable Emulation Model for the D-algorithm. 1172-1176
  
• Akira Miyashita, Toshihito Fujiwara, Tsutomu Maruyama:
  A Placement/Routing Approach for FPGA Accelerators. 1177-1182
  

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