• 
  Tero Rissa, Steven J. E. Wilton, Philip Heng Wai Leong (Eds.): Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005. IEEE 2005 ISBN 0-7803-9362-7

Embedded Soft Processors

• 
  Robert G. Dimond, Oskar Mencer, Wayne Luk: CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools. 1-6
• 
  Zhiguo Ge, Hock-Beng Lim, Weng-Fai Wong: A Reconfigurable Instruction Memory Hierarchy for Embedded Systems. 7-12
• 
  Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello: Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. 13-18

Logic Synthesis

• 
  Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: FPGA PLB Evaluation using Quantified Boolean Satisfiability. 19-24
• 
  Carlos Morra, Jürgen Becker, Mauricio Ayala-Rincón, Reiner W. Hartenstein: FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations. 25-30
• 
  Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown: Post-Placement BDD-Based Decomposition for FPGAs. 31-38

Networking Applications 1

• 
  Giorgos Papadopoulos, Dionisios N. Pnevmatikatos: Hashing + Memory = Low Cost, Exact Pattern Matching. 39-44
• 
  Yutaka Sugawara, Mary Inaba, Kei Hiraki: High-speed and Memory Efficient TCP Stream Scanning using FPGA. 45-50
• 
  Todd S. Sproull, Gordon J. Brebner, Christopher E. Neely: Mutable Codesign for Embedded Protocol Processing. 51-56

Chip Communication Architectures

• 
  Chi-Wei Wang, Nicholas P. Carter, Richard B. Kujoth, Jeffrey J. Cook, Derek B. Gottlieb: Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor. 57-64
• 
  Hisashi Tsukiashi, Masahiro Iida, Toshinori Sueyoshi: Applying the Small-World Network to Routing Structure of FPGAs. 65-70

CAD for Coarse-Grained Logic

• 
  Michael B. Healy, Mongkol Ekpanyapong, Sung Kyu Lim: MILP-based Placement and Routing for Dataflow Architecture. 71-76
• 
  Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung: Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. 77-82

SAT Solvers and Neural Networks

• 
  Kenji Kanazawa, Tsutomu Maruyama: An FPGA Solver for WSAT Algorithms. 83-88
• 
  Pedro Domingos, Fernando M. Silva, Horácio C. Neto: An Efficient and Scalable Architecture for Neural Networks with Backpropagation Learning. 89-94

Chip Architectures

• 
  Mark Holland, Scott Hauck: Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC. 95-100
• 
  Chao You, Jong-Ru Guo, Michael Chu, Russell P. Kraft, Bryan S. Goda, John F. McDonald: A 11 GHz FPGA with Test Applications. 101-105
• 
  Francisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng Mei: Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes. 106-111

Arithmetic

• 
  Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: Power and Area Optimization for Multiple Restricted Multiplication. 112-117
• 
  Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler: Programmable Numerical Function Generators: Architectures and Synthesis Method. 118-123
• 
  Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides: Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. 124-129

Video Processing Applications 1

• 
  Marek Gorgon, Slawomir Cichon, Miroslaw Pac: Real-time Handel-C Based Implementation of DV Decoder. 130-135
• 
  Najeem Lawal, Benny Thörnberg, Mattias O'Nils: Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems. 136-141
• 
  Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk: Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing. 142-147

Run-Time Reconfigurable Architectures and Applications

• 
  John Esquiagola, Guilherme Ozari, Marcio Yukio Teruya, Marius Strum, Wang Jiang Chau: A Dynamically Reconfigurable Bluetooth Base Band Unit. 148-152
• 
  Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. 153-158

Routing Characterization

• 
  Andy Gean Ye, Jonathan Rose: Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks. 159-166
• 
  Shankar Balachandran, Dinesh Bhatia: Timing Aware Interconnect Prediction Models for FPGAs. 167-172

Multidimensional Processing

• 
  Shingo Masuno, Tsutomu Maruyama, Yoshiki Yamaguchi, Akihiko Konagaya: Multidimensional Dynamic Programming for Homology Search. 173-178
• 
  Hiroaki Niitsuma, Tsutomu Maruyama: Real-time Generation of Three-Dimensional Motion Fields. 179-184
• 
  Tobias Oppold, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel, Urs Kanus, Wolfgang Straßer: Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures. 185-190

Network on Chip Architectures

• 
  Clint Hilton, Brent E. Nelson: A Flexible Circuit-Switched NOC for FPGA-Based Systems. 191-196
• 
  Pascal T. Wolkotte, Gerard J. M. Smit, Jens E. Becker: Energy-Efficient NoC for Best-Effort Communication. 197-202
• 
  Heikki Kariniemi, Jari Nurmi: Fault-Tolerant XGFT Network-On-Chip for Multi-Processor System-on-Chip Circuits. 203-210

Tools and Methods for Run-Time Reconfiguration

• 
  N. Pete Sedcole, Brandon Blodget, Tobias Becker, James Anderson, Patrick Lysaght: Modular Partial Reconfiguration in Virtex FPGAs. 211-216
• 
  Nico Kasprzyk, Jan van der Veen, Andreas Koch: Configuration Merging for Adaptive Computer Applications. 217-222
• 
  Heiko Kalte, Mario Porrmann: Context Saving and Restoring for Multitasking in Reconfigurable Systems. 223-228

Implementation Techniques

• 
  Dusan Suvakovic, Ilija Hadzic: An FPGA Application with High Speed Serial Transceiver Running at Sub-nominal Rate. 229-234
• 
  Valery Sklyarov, Iouliia Skliarova, Bruno Figueiredo Pimentel: FPGA-based implementation and comparison of recursive and iterative algorithms. 235-240
• 
  Marc Bautista-Palacios, Luis Baldez, Jordi Sempere-Agulló, Atilà Herms-Berenguer, Francisco Cardells-Tormo, Pep-Lluis Molinet: Configurable Hardware/Software Architecture for Data Acquisition: Implementation on FPGA. 241-246

Defect Tolerance

• 
  Zohair Hyder, John Wawrzynek: Defect Tolerance in Multiple-FPGA Systems. 247-254
• 
  Anthony J. Yu, Guy G. Lemieux: Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement. 255-262

Compilation Methods 1

• 
  Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides: Heterogeneity Exploration for Multiple 2D Filter Designs. 263-268
• 
  Seppo Virtanen, Dragos Truscan, Jani Paakkulainen, Jouni Isoaho, Johan Lilius: Highly Automated FPGA Synthesis of Application-Specific Protocol Processors. 269-274

Cryptography Applications

• 
  Guanglie Zhang, Philip Heng Wai Leong, Dong-U Lee, John D. Villasenor, Ray C. C. Cheung, Wayne Luk: Ziggurat-based Hardware Gaussian Random Number Generator. 275-280
• 
  Wenhai Fang, Thomas Johansson, Lambert Spaanenburg: Snow 2.0 IP Core for Trusted Hardware. 281-286

Asynchronous Architectures

• 
  Xin Jia, Ranga Vemuri: A Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation. 287-292
• 
  Laurent Fesquet, Marc Renaudin: A Programmable Logic Architecture for Prototyping Clockless Circuits. 293-298
• 
  Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin: GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. 299-304

Compilation Methods 2

• 
  Peter Jamieson, Jonathan Rose: A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. 305-310
• 
  Henry Styles, Wayne Luk: Compilation and Management of Phase-Optimized Reconfigurable Systems. 311-316
• 
  Justin L. Tripp, Kristopher D. Peterson, Christine Ahrens, Jeffrey D. Poznanovic, Maya Gokhale: Trident: An FPGA Compiler Framework for Floating-Point Algorithms. 317-322

Bio-Inspired Computing

• 
  Iosifina Pournara, Christos-Savvas Bouganis, George A. Constantinides: FPGA-Accelerated Reconstruction of Gene Regulatory Networks. 323-328
• 
  Peter Zipf, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred Glesner: Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata. 329-334
• 
  Peter Zipf, Oliver Soffke, Andre Schumacher, Clemens Schlachta, Radu Dogaru, Manfred Glesner: A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata. 335-340

System Architecture Exploration and Evaluation

• 
  Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: An Analytical Approach to Generation and Exploration of Reconfigurable Architectures. 341-346
• 
  Hideharu Amano, Shohei Abe, Katsuaki Deguchi, Yohei Hasegawa: An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration? 347-352
• 
  Miyoshi Saito, Hisanori Fujisawa, Nobuo Ujiie, Hideki Yoshizawa: Cluster Architecture for Reconfigurable Signal Processing Engine for Wireless Communication. 353-359

Communication Synthesis and High Level Design

• 
  Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere: Communication Synthesis in a multiprocessor environment. 360-365
• 
  Tsuyoshi Hamada, Naohito Nakasato: PGR: A Software Package for Reconfigurable Super-Computing. 366-373
• 
  Sujan Pandey, Manfred Glesner, Max Mühlhäuser: On-Chip Communication Topology Synthesis for a Shared Memory Architecture. 374-379

MPEG Applications

• 
  Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko Hännikäinen, Timo D. Hämäläinen: A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC. 380-385
• 
  Michael Janiaut, Camel Tanougast, Hassan Rabah, Yves Berviller, Christian Mannino, Serge Weber: Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis. 386-390
• 
  Kristof Denolf, Adrian Chirila-Rus, Robert D. Turney, Paul R. Schumacher, Kees A. Vissers: Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs. 391-396

Fault Tolerant Architectures and Systems

• 
  Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes: An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation. 397-402
• 
  Olivier Héron, Talal Arnaout, Hans-Joachim Wunderlich: On the Reliability Evaluation of SRAM-Based FPGA Designs. 403-408
• 
  Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. 409-414

Placement

• 
  Pritha Banerjee, Subhasis Bhattacharjee, Susmita Sur-Kolay, Sandip Das, Subhas C. Nandy: Fast FPGA Placement using Space-filling Curve. 415-420
• 
  I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David V. Anderson: Hierarchical Placement for Large-scale FPAA. 421-426
• 
  Akshay Sharma, Carl Ebeling, Scott Hauck: Architecture-Adaptive Routability-Driven Placement for FPGAs. 427-432

Security Attacks and Detection

• 
  Vincent Carlier, Hervé Chabanne, Emmanuelle Dottax, Hervé Pelletier: Generalizing Square Attack using Side-Channels of an AES Implementation on an FPGA. 433-437
• 
  David Nguyen, Gokhan Memik, Seda Ogrenci Memik, Alok N. Choudhary: Real-Time Feature Extraction for High Speed Networks. 438-443
• 
  Sherif Yusuf, Wayne Luk: Bitwise Optimised CAM for Network Intrusion Detection Systems. 444-449

Video Processing Architectures and Systems

• 
  Shrutisagar Chandrasekaran, Abbes Amira: High Speed / Low Power Architectures for the Finite Radon Transform. 450-455
• 
  Sebastien Wong, Mark Jasiunas, David A. Kearney: Towards a Reconfigurable Tracking System. 456-462
• 
  Javier Díaz, Eduardo Ros, Sonia Mota, Eva M. Ortigosa, Begoña del Pino: High Performance Stereo Computation Architecture. 463-498

Emulation and Simulation

• 
  Qiang Qiang, Daniel G. Saab, Jacob A. Abraham: An Emulation Model for Sequential ATPG-Based Bounded Model Checking. 469-474
• 
  Yongfeng Gu, Tom Van Court, Martin C. Herbordt: Accelerating Molecular Dynamics Simulations With Configurable Circuits. 475-480
• 
  Victor Gonçalves, José T. de Sousa, Fernando M. Gonçalves: A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits. 481-486

Networking Applications 2

• 
  Kaushik Ravindran, Nadathur Satish, Yujia Jin, Kurt Keutzer: An FPGA-based Soft Multiprocessor System for IPv4 Packet Forwarding. 487-492
• 
  Haoyu Song, Todd S. Sproull, Michael Attig, John W. Lockwood: Snort Offloader: A Reconfigurable Hardware NIDS Filter. 493-498
• 
  Charles M. Kastner, G. Adam Covington, Andrew A. Levine, John W. Lockwood: HAIL: A Hardware-Accelerated Algorithm for Language Identification. 499-504

Poster Session 1

• 
  Rawat Siripokarpirom: A Run-Time Reconfigurable Hardware Infrastructure for IP-Core Evaluation and Test. 505-508
• 
  Sinan Yalcin, Hasan F. Ates, Ilker Hamzaoglu: A High Performance Hardware Architecture for an SAD Reuse based Hierarchical Motion Estimation Algorithm for H.264 Video Coding. 509-514
• 
  Elias Todorovich, Fabian Angarita, Javier Valls, Eduardo I. Boemo: Statistical Power Estimation for FPGA. 515-518
• 
  Georg Acher, Rainer Buchty, Carsten Trinitis: CPU-independent Assembler in an FPGA. 519-522
• 
  Carlos Leong, P. Bento, Pedro Rodrigues, Andreia Trindade, J. C. Silva, Pedro Lousã, Joel Rego, J. Nobre, João Varela, João Paulo Teixeira, Isabel C. Teixeira: Design and Test Methodology for a Reconfigurable PEM Data Acquisition Electronics System. 523-526
• 
  Ronald Hecht, Stephan Kubisch, Andreas Herrholtz, Dirk Timmermann: Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs. 527-530
• 
  Antonio García, Javier Ramírez, Uwe Meyer-Bäse, Encarnación Castillo, Antonio Lloris-Ruíz: Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks. 531-534
• 
  Fabian Angarita, A. Perez-Pascual, T. Sansaloni, Javier Valls: Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates. 535-538
• 
  David Narh Amanor, Viktor Bunimov, Christof Paar, Jan Pelzl, Manfred Schimmler: Efficient Hardware Architectures for Modular Multiplication on FPGAs. 539-542
• 
  Jawad Khan, Ranga Vemuri: Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes. 543-546
• 
  José-Javier Martínez, F. Javier Toledo, F. Javier Garrigós, José Manuel Ferrández de Vicente: FPGA Implementation of an Area-Time Efficient FIR Filter Core Using a Self-Clocked Approach. 547-550
• 
  Artur Schiefer, Udo Kebschull: Optimization of Start-Up Time and Quiescent Power Consumption of FPGAs. 551-554
• 
  Yonghong Xu, Mohammed A. S. Khalid: QPF: Efficient Quadratic Placement for FPGAs. 555-558
• 
  Jacobo Álvarez, Jorge Marcos, Santiago Fernandez: Safe PLD-based Programmable Controllers. 559-562
• 
  Juanjo Noguera, Rosa M. Badia: Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable Architectures. 563-567

Poster Session 2

• 
  Klaus Danne, Marco Platzner: A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware. 568-573
• 
  Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano: A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA. 574-577
• 
  Francisco Cardells-Tormo, Pep-Lluis Molinet, Jordi Sempere-Agulló, Luis Baldez, Marc Bautista-Palacios: Area-Efficient 2-D Shift-Variant Convolvers for FPGA-based Digital Image Processing. 578-581
• 
  Martin J. Pearson, Chris Melhuish, Anthony G. Pipe, Mokhtar Nibouche, Ian Gilhespy, Kevin N. Gurney, Benjamin Mitchinson: Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network Processor. 582-585
• 
  Hendrik Lange, Hartmut Schröder: Evaluation Strategies for Coarse Grained Reconfigurable Architectures. 586-589
• 
  Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl: Figaro - An Automatic Tool Flow for Designs with Dynamic Reconfiguration. 590-593
• 
  Maurice Keller, Tim Kerins, William P. Marnane: FPGA Implementation of a GF(2^4M) Multiplier for use in Pairing Based Cryptosystems. 594-597
• 
  Xavier Revés, Vuk Marojevic, Ramon Ferrús, Antoni Gelonch: FPGA's Middleware for Software Defined Radio Applications. 598-601
• 
  Dragomir Milojevic: Implementation of Ranking Filters on General Purpose and Reconfigurable Architecture Based on High Density FPGA Devices. 602-605
• 
  Tapani Ahonen, Jari Nurmi: Integration of a NoC-Based Multimedia Processing Platform. 606-611
• 
  Tom Van Court, Martin C. Herbordt: LAMP: A Tool Suite for Families of FPGA-Based Application Accelerators. 612-617
• 
  Sajid Baloch, Imran Ahmed, Tughrul Arslan, Adrian Stoica: Low Power Domain-Specific Reconfigurable Array for Discrete Wavelet Transforms Targeting Multimedia Applications. 618-621
• 
  Bingfeng Mei, Francisco-Javier Veredas, Bart Masschelein: Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture. 622-625
• 
  Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides: Parameterized Logic Power Consumption Models for FPGA based Systems. 626-629
• 
  Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis: Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs. 630-635

Poster Session 3

• 
  Usama Malik, Oliver Diessel: A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs. 636-639
• 
  Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki: A Novel Toolset for the Development of FPGA-like Reconfigurable Logic. 640-643
• 
  Ioannis Sourdis, Dionisios N. Pnevmatikatos, Stephan Wong, Stamatis Vassiliadis: A Reconfigurable Perfect-Hashing Scheme for Packet Inspection. 644-647
• 
  Yang Qu, Juha-Pekka Soininen, Jari Nurmi: An Efficient Approach to Hide the Run-Time Reconfiguration from SW Applications. 648-653
• 
  Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann: An FPGA Network Architecture for Accelerating 3DES - CBC. 654-657
• 
  Kostas Siozios, Konstantinos Tatas, George Koutroumpezis, D. J. Soudris, Adonios Thanailakis: An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. 658-661
• 
  Boris Ratchev, Mike Hutton, David Mendel: Coping With Uncertainty in FPGA Architecture Design. 662-665
• 
  Naoki Iwanaga, Yuichiro Shibata, Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri: Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA. 666-669
• 
  Jean-Pierre Deschamps, Gustavo Sutter: Finite Field Division Implementation. 670-674
• 
  Philippe Faes, Mark Christiaens, Dries Buytaert, Dirk Stroobandt: FPGA-Aware Garbage Collection in Java. 675-680
• 
  Allen Michalski, Kris Gaj, Duncan A. Buell: High-Throughput Reconfigurable Computing: A Design Study of an IDEA Encryption Cryptosystem on the SRC-6e Reconfigurable Computer. 681-686
• 
  Nicolas Bruchon, Gaston Cambon, Lionel Torres, Gilles Sassatelli: Magnetic remanent memory structures for dynamically reconfigurable fine grain FPGA. 687-690
• 
  Kuen Hung Tsoi, Philip Heng Wai Leong: Mullet - A Parallel Multiplier Generator. 691-694
• 
  Martin Zádník, Tomas Pecenka, Jan Korenek: NetFlow Probe Intended for High-Speed Networks. 695-698
• 
  Zdenek Pohl, Premysl Sucha, Jiri Kadlec, Zdenek Hanzálek: Performance Tuning of Iterative Algorithms in Signal Processing. 699-702
• 
  Pascal Benoit, Jürgen Becker, Michel Robert, Lionel Torres, Gilles Sassatelli, Gaston Cambon: Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors. 703-706

PhD Forum

• 
  Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis: A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow. 707-708
• 
  Frank Honoré: A Power-Performance Scalable FPGA Using Configurable Voltage Domains and Design Mapping Tool. 709-710
• 
  Luis E. Cordova, Duncan A. Buell: An Approach to Scalable Molecular Dynamics Simulation Using Supercomputing Adaptive Processing Elements. 711-712
• 
  Kuen Hung Tsoi: Computer Arithmetic Synthesis Technologies on Reconfigurable Platforms. 713-714
• 
  Chun Te Ewe: Dual FiXed-point : An Efficient Alternative to Floating-point Computation for DSP applications. 715-716
• 
  Florian Dittmann: Efficient Execution on Reconfigurable Devices Using Concepts of Pipelining. 717-718
• 
  Alastair M. Smith: Exploration of Heterogeneous Reconfigurable Architectures. 719-720
• 
  Fernando Pardo, P. López, Diego Cabello, M. Balsi: FPGA Finite-Difference Time-Domain solver for thermal simulation. 721-722
• 
  F. Javier Toledo, José-Javier Martínez, F. Javier Garrigós, José Manuel Ferrández de Vicente: FPGA Implementation of an Augmented Reality Application for Visually Impaired People. 723-724
• 
  Nicola Campregher: FPGA Interconnect Fault tolerance. 725-726
• 
  Kurian Oommen, David Harle: Hardware Emulation of a Network on Chip Architecture based on a Clockwork Routed Manhattan Street Network. 727-728
• 
  János Lazányi: Instruction Set Extension Using Microblaze Processor. 729-730
• 
  Lesley Shannon, Paul Chow: Leveraging Reconfigurability in the Design Process. 731-732
• 
  Martin J. Pearson: MechanoProcessor: Modelling the Rodent Whisker Sensory System using FPGA. 733-734
• 
  Rajarshee P. Bharadwaj: Next Generation Architectures and CAD for Power Aware Programmable Fabrics. 735-738
• 
  Renqiu Huang, Ranga Vemuri: PAHLS: Towards Run-Time Synthesis for FPGAs. 739-740
• 
  David Nguyen: Reconfigurable Architectures for Real-Time Network Anomaly Detection. 741-742
• 
  Hiren Joshi, S. S. Verma, G. K. Sharma: Requested-QoS Driven Runtime Reconfiguration of Mobile Devices. 743-744
• 
  Alexander Thomas: Design of a Dynamic Reconfigurable Multi-Grained Hardware Architecture with Adaptive Runtime Routing. 745-746
• 
  Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Testing Superscalar Processors in Functional Mode. 747-750