15. FPL 2005: Tampere, Finland

Embedded Soft Processors

Logic Synthesis

Networking Applications 1

Chip Communication Architectures

CAD for Coarse-Grained Logic

SAT Solvers and Neural Networks

Chip Architectures

Arithmetic

Video Processing Applications 1

Run-Time Reconfigurable Architectures and Applications

Routing Characterization

Multidimensional Processing

Network on Chip Architectures

Tools and Methods for Run-Time Reconfiguration

Implementation Techniques

Defect Tolerance

Compilation Methods 1

Cryptography Applications

Asynchronous Architectures

Compilation Methods 2

Bio-Inspired Computing

System Architecture Exploration and Evaluation

Communication Synthesis and High Level Design

MPEG Applications

Fault Tolerant Architectures and Systems

Placement

Security Attacks and Detection

Video Processing Architectures and Systems

Emulation and Simulation

Networking Applications 2

Poster Session 1

Poster Session 2

Poster Session 3

PhD Forum