21. FPL 2011:
Chania, Crete, Greece
International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece.
IEEE 2011, ISBN 978-1-4577-1484-9
- Frederik Grüll, Manfred Kirchgessner, Rainer Kaufmann, Michael Hausmann, Udo Kebschull:
Accelerating Image Analysis for Localization Microscopy with FPGAs.
1-5

- Qiwei Jin, Wayne Luk, David B. Thomas:
Unifying Finite Difference Option-Pricing for Hardware Acceleration.
6-9

- Martin Schoeberl:
Leros: A Tiny Microcontroller for FPGAs.
10-14

- Matina Lakka, Eftichios Koutroulis, Apostolos Dollas:
Design of a High Switching Frequency FPGA-Based SPWM Generator for DC/AC Inverters.
15-19

- Florent Bruguier, Pascal Benoit, Philippe Maurine, Lionel Torres:
A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis.
20-23

- Jack Sampson, Manish Arora, Nathan Goulding-Hotta, Ganesh Venkatesh, Jonathan Babb, Vikram Bhatt, Steven Swanson, Michael Bedford Taylor:
An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors.
24-29

- Harry Sidiropoulos, Kostas Siozios, Dimitrios Soudris:
A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs.
30-33

- Takahiro Watanabe, Minoru Watanabe:
Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory.
34-37

- Kenji Kanazawa, Tsutomu Maruyama:
An FPGA Solver for SAT-Encoded Formal Verification Problems.
38-43

- Will X. Y. Li, Rosa H. M. Chan, Wei Zhang, C. W. Yu, Ray C. C. Cheung, Dong Song, Theodore W. Berger:
FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Activities.
44-49

- Jason Cong, Muhuan Huang, Yi Zou:
Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms.
50-57

- Bill Teng, Jason Helge Anderson:
Latch-Based Performance Optimization for FPGAs.
58-63

- Subhrashankha Ghosh, Brent E. Nelson:
XDL-Based Module Generators for Rapid FPGA Design Implementation.
64-69

- Rehan Ahmed, Peter Hallschmid:
Modeling and Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-Based Systems Using Stochastic Networks.
70-75

- William V. Kritikos, Yamuna Rajasekhar, Andrew G. Schmidt, Ron Sass:
A Radix Tree Router for Scalable FPGA Networks.
76-81

- Ye Lu, John V. McCanny, Sakir Sezer:
Generic Low-Latency NoC Router Architecture for FPGA Computing Systems.
82-89

- Giorgos Dimitrakopoulos, Christoforos Kachris, Emmanouil Kalligeros:
Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks.
90-96

- Hiroaki Inoue, Takashi Takenaka, Masato Motomura:
20Gbps C-Based Complex Event Processing.
97-102

- Joachim Meyer, Juanjo Noguera, Michael Hübner, Rodney Stewart, Jürgen Becker:
Embedded Systems Start-Up under Timing Constraints on Modern FPGAs.
103-109

- Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang:
Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method.
110-115

- Xiang Tian, Christos-Savvas Bouganis:
A Run-Time Adaptive FPGA Architecture for Monte Carlo Simulations.
116-122

- Benjamin Thielmann, Jens Huthmann, Andreas Koch:
Precore - A Token-Based Speculation Architecture for High-Level Language to Hardware Compilation.
123-129

- Jocelyn Sérot, François Berry, Sameer Ahmed:
Implementing Stream-Processing Applications on FPGAs: A DSL-Based Approach.
130-137

- Mário P. Véstias, Horácio C. Neto:
Revisiting the Newton-Raphson Iterative Method for Decimal Division.
138-143

- Yuanxi Peng, Manuel Saldaña, Paul Chow:
Hardware Support for Broadcast and Reduce in MPSoC.
144-150

- Abhranil Maiti, Logan McDougall, Patrick Schaumont:
The Impact of Aging on an FPGA-Based Physical Unclonable Function.
151-156

- Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama:
An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators.
157-161

- Nicolas Sklavos:
Multi-module Hashing System for SHA-3 & FPGA Integration.
162-166

- Christos Kyrkou, Christos Ttofis, Theocharis Theocharides:
FPGA-Accelerated Object Detection Using Edge Information.
167-170

- Brahim Al Farisi, Karel Heyse, Karel Bruneel, Dirk Stroobandt:
Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs.
171-176

- Juan Antonio Clemente, Vincenzo Rana, Donatella Sciuto, Ivan Beretta, David Atienza:
A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware.
177-180

- Diana Göhringer, Stephan Werner, Michael Hübner, Jürgen Becker:
RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC.
181-184

- Andreas Agne, Marco Platzner, Enno Lübbers:
Memory Virtualization for Multithreaded Reconfigurable Hardware.
185-188

- Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures.
189-194

- Krzysztof Kepa, Fearghal Morgan, Peter Athanas:
ERDB: An Embedded Routing Database for Reconfigurable Systems.
195-200

- Oguzhan Erdem, Hoang Le, Viktor K. Prasanna:
Clustered Hierarchical Search Structure for Large-Scale Packet Classification on FPGA.
201-206

- Mohammed M. Farag, Lee W. Lerner, Cameron D. Patterson:
Thwarting Software Attacks on Data-Intensive Platforms with Configurable Hardware-Assisted Application Rule Enforcement.
207-212

- Thilan Ganegedara, Hoang Le, Viktor K. Prasanna:
Towards On-the-Fly Incremental Updates for Virtualized Routers on FPGA.
213-218

- Dang Ba Khac Trieu, Tsutomu Maruyama:
An Implementation of the Mean Shift Filter on FPGA.
219-224

- Hadi Parandeh-Afshar, Paolo Ienne:
Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs.
225-231

- Hong Diep Nguyen, Bogdan Pasca, Thomas B. Preußer:
FPGA-Specific Arithmetic Optimizations of Short-Latency Adders.
232-237

- Harry Sidiropoulos, Kostas Siozios, Dimitrios Soudris:
A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs.
238-243

- Daniel Lo, Greg Malysa, G. Edward Suh:
FlexCache: Field Extensible Cache Controller Architecture Using On-chip Reconfigurable Fabric.
244-251

- Yuanwu Lei, Yong Dou, Jie Zhou, Sufeng Wang:
VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic.
252-257

- Emmanuel Seguin, Russell Tessier, Eric J. Knapp, Robert W. Jackson:
A Dynamically-Reconfigurable Phased Array Radar Processing System.
258-263

- Pavlos Malakonakis, Apostolos Dollas:
Exploitation of Parallel Search Space Evaluation with FPGAs in Combinatorial Problems: The Eternity II Case.
264-268

- Abdulkadir Akin, Onur Can Ulusel, Tevfik Zafer Ozcan, Gokhan Sayilar, Ilker Hamzaoglu:
A Novel Power Reduction Technique for Block Matching Motion Estimation Hardware.
269-272

- Mark Hamilton, William P. Marnane, Arnaud Tisserand:
A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p Values.
273-276

- Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich:
Stress-Aware Module Placement on Reconfigurable Devices.
277-281

- Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He:
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.
282-285

- Dirk Koch, Jim Torresen:
A Routing Architecture for Mapping Dataflow Graphs at Run-Time.
286-290

- Kazuki Inoue, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
An Easily Testable Routing Architecture and Efficient Test Technique.
291-294

- Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Raul Torrego, Imanol Martinez:
Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing Fully Relocatable Hardware Tasks in Xilinx FPGAs.
295-300

- Vasco Bexiga, Carlos Leong, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira, María Dolores Valdés, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas:
Performance Failure Prediction Using Built-In Delay Sensors in FPGAs.
301-304

- Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong:
A Model for Matrix Multiplication Performance on FPGAs.
305-310

- Yong Cheol Peter Cho, Sungmin Bae, Yongseok Jin, Kevin M. Irick, Vijaykrishnan Narayanan:
Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA.
311-316

- Christian Leber, Benjamin Geib, Heiner Litz:
High Frequency Trading Acceleration Using FPGAs.
317-322

- Edward A. Stott, Peter Y. K. Cheung:
Improving FPGA Reliability with Wear-Levelling.
323-328

- Abdulazim Amouri, Mehdi Baradaran Tahoori:
A Low-Cost Sensor for Aging and Late Transitions Detection in Modern FPGAs.
329-335

- Marcel Gort, Jason Helge Anderson:
Reducing FPGA Router Run-Time through Algorithm and Architecture.
336-342

- Paul Schumacher, Pradip Jha, Sudha Kuntur, Tim Burke, Alan Frost:
Fast RTL Power Estimation for FPGA Designs.
343-348

- Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings:
RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs.
349-355

- Michel A. Kinsy, Michael Pellauer, Srinivas Devadas:
Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System.
356-362

- Daniel Llamocca, Cesar Carranza, Marios S. Pattichis:
Separable FIR Filtering in FPGA and GPU Implementations: Energy, Performance, and Accuracy Considerations.
363-368

- Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Teresa Cervero, Sebastián López, Gustavo Marrero Callicó, Roberto Sarmiento:
Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs.
369-375

- Ismail San, Nuray At:
Compact Hardware Architecture for Hummingbird Cryptographic Algorithm.
376-381

- Surapong Pongyupinpanich, Manfred Glesner:
Pipelined Floating-Point Architecture for a Phase and Magnitude Detector Based on CORDIC.
382-384

- Cinzia Bernardeschi, Luca Cassano, Andrea Domenici:
Failure Probability and Fault Observability of SRAM-FPGA Systems.
385-388

- Diego González, Guillermo Botella Juan, Soumak Mokheerje, Uwe Meyer-Bäse:
FPGA-Based Acceleration of Block Matching Motion Estimation Techniques.
389-392

- Bogdan Alecsa, Alexandru Onea:
An Optimized FPGA Implementation of the Modified Space Vector Modulation Algorithm for AC Drives Control.
393-395

- François Philipp, Manfred Glesner:
Mechanisms and Architecture for the Dynamic Reconfiguration of an Advanced Wireless Sensor Node.
396-398

- Kurt Schwenk, Katharina Goetz, Maria von Schoenermark, Felix Huber:
Real-Time Evaluation of Remote Sensing Data on Board of Satellites.
399-400

- Jan Kloub, Tomas Mazanec, Antonin Hermanek:
Heterogeneous Platform for Stream Based Applications on FPGAs.
401-404

- Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson:
Implementation in FPGA of Address-Based Data Sorting.
405-410

- Grigorios Chrysos, Panagiotis Dagritzikos, Ioannis Papaefstathiou, Apostolos Dollas:
Novel and Highly Efficient Reconfigurable Implementation of Data Mining Classification Tree.
411-416

- Nikolaos Alachiotis, Alexandros Stamatakis:
FPGA Acceleration of the Phylogenetic Parsimony Kernel?
417-422

- Xun Chen, Jianwen Zhu, Minxuan Zhang:
Timing-Driven Routing of High Fanout Nets.
423-428

- Stefan Wildermann, Jürgen Teich, Daniel Ziener:
Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs.
429-434

- Seong-I. Lei, Wai-Kei Mak:
Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign.
435-440

- Kashfia Haque, Paul Beckett:
A Radiation Hard Lut Block with Auto-Scrubbing.
441-446

- Zhen Wang, Ding Xie, Jinmei Lai:
FPGA Interconnect Architecture Exploration Based on a Statistical Model.
447-452

- Fatemeh Eslami, Mihai Sima:
Capacitive Boosting for FPGA Interconnection Networks.
453-458

- Orsalia Georgia Hazapis, Elias S. Manolakos:
Scalable FRM-SSA SoC Design for the Simulation of Networks with Thousands of Biochemical Reactions in Real Time.
459-463

- Yi-Gang Tai, Kleanthis Psarris, Chia-Tien Dan Lo:
Synthesizing Tiled Matrix Decomposition on FPGAs.
464-469

- Lintao Cui, Jing Chen, Yu Hu, Jinjun Xiong, Zhe Feng, Lei He:
Acceleration of Multi-agent Simulation on FPGAs.
470-473

- Imre Pechan, Béla Féher:
Molecular Docking on FPGA and GPU Platforms.
474-477

- Keisuke Dohi, Yuji Yorita, Yuichiro Shibata, Kiyoshi Oguri:
Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation.
478-481

- Zhe Feng, Naifeng Jing, GengSheng Chen, Yu Hu, Lei He:
IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs.
482-485

- Zdenek Pohl, Milan Tichý:
Resource Management for the Heterogeneous Arrays of Hardware Accelerators.
486-489

- Takefumi Miyoshi, Hideyuki Kawashima, Yuta Terada, Tsutomu Yoshinaga:
A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine.
490-495

- Fearghal Morgan, Seamus Cawley, Frank Callaly, Shane Agnew, Patrick Rocke, Martin O'Halloran, Nina Drozd, Krzysztof Kepa, Brian McGinley:
Remote FPGA Lab with Interactive Control and Visualisation Interface.
496-499

- Lubos Gaspar, Viktor Fischer, Lilian Bossuet, Milos Drutarovský:
Cryptographic Extension for Soft General-Purpose Processors with Secure Key Management.
500-505

- Rajesh Velegalati, Jens-Peter Kaps:
Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs.
506-511

- Paulo Proenca, Ricardo Chaves:
Compact CLEFIA Implementation on FPGAS.
512-517

- Yousef Iskander, Cameron D. Patterson, Stephen D. Craven:
Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug.
518-523

- Eddie Hung, Steven J. E. Wilton:
Speculative Debug Insertion for FPGAs.
524-531

- Cristiana Bolchini, Antonio Miele, Chiara Sandionigi:
Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems.
532-538

- Haile Yu, Qiang Xu, Philip Heng Wai Leong:
On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry.
539-544

- Xinyu Niu, Kuen Hung Tsoi, Wayne Luk:
Reconfiguring Distributed Applications in FPGA Accelerated Cluster with Wireless Networking.
545-550

- Lyonel Barthe, Luis Vitório Cargnini, Pascal Benoit, Lionel Torres:
Optimizing an Open-Source Processor for FPGAs: A Case Study.
551-556

Last update Thu May 23 16:49:38 2013
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