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ORCIDFPT 2003: Tokyo, Japan
- Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, Tokyo, Japan, FPT 2003, December 15-17, 2003. IEEE 2003
Keynotes / Invited Papers
- Phil Bishop, Chris Sullivan:
A reconfigurable future. 2-7 - Naotoshi Nojiri, Tadatoshi Ishii:
Seamless top-down flow for quick trial of HW/SW co-design. 8-12 - Gordon J. Brebner
, Delon Levi:
Networking on chip with platform FPGAs. 13-20 - Minoru Fujishima:
FPGA-based high-speed emulator of quantum computing. 21-26
Applications
- Riad Stefo, Jörg Schreiter, Jens-Uwe Schluessler, René Schüffny:
High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications. 28-34 - Aziz Ahmedsaid, Abbes Amira, Ahmed Bouridane:
Improved SVD systolic array and implementation on FPGA. 35-42
Cryptography & Computer Security
- Yoshinori Adachi, Kenichiro Ishikawa, Satoshi Tsutsumi, Hideharu Amano:
An implementation of the Rijndael on Async-WASMII. 44-51 - S. H. Tang, K. S. Tsui, Philip Heng Wai Leong:
Modular exponentiation using parallel multipliers. 52-59 - Nghi Nguyen, Kris Gaj, David Caliga, Tarek A. El-Ghazawi:
Implementation of Elliptic Curve Cryptosystems on a reconfigurable computer. 60-67 - Christopher R. Clark, David E. Schimmel:
A pattern-matching co-processor for network intrusion detection systems. 68-74
Computer Arithmetic
- Barry Lee, Neil Burgess:
A parallel look-up logarithmic number system addition/subtraction scheme for FPGA. 76-83 - Chun Hok Ho, Kuen Hung Tsoi, Jackson H. C. Yeung, Yuet Ming Lam, Kin-Hong Lee, Philip Heng Wai Leong, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner:
Arbitrary function approximation in HDLs with application to the N-body problem. 84-91 - Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung:
Hierarchical segmentation schemes for function evaluation. 92-99
Signal Processing
- Isa Servan Uzun, Abbes Amira, Ahmed Bouridane:
FPGA implementations of fast fourier transforms for real-time signal and image processing. 102-109 - Ray C. C. Cheung, Kong-Pang Pun, Steve C. L. Yuen, Kuen Hung Tsoi, Philip Heng Wai Leong:
An FPGA-based re-configurable 24-bit 96kHz sigma-delta audio DAC. 110-117 - Thilo Pionteck, Lukusa D. Kabulepa, Clemens Schlachta, Manfred Glesner:
Reconfiguration requirements for high speed wireless communication systems. 118-125 - Jihan Zhu, Peter Sutton:
An FPGA implementation of Kak's instantaneously-trained, Fast-Classification neural networks. 126-133
Runtime Reconfiguration
- Yoshiki Nakane, Kouichi Nagami, Tsunemichi Shiozawa, Akira Nagoya:
Concept and implementation of run-time resource management system operating on autonomously reconfigurable architecture. 136-143 - T. K. Lee, Arran Derbyshire, Wayne Luk, Peter Y. K. Cheung:
High-level language extensions for run-time reconfigurable systems. 144-151
Runtime Reconfiguration
- Steven W. Oldridge, Steven J. E. Wilton:
Placement and routing for FPGA architectures supporting wide shallow memories. 154-161 - Andy Yan, Steven J. E. Wilton:
Product-term based synthesizable embedded programmable logic cores. 162-169 - Catherine G. Wong, Alain J. Martin, Peter Thomas:
An architecture for asynchronous FPGAs. 170-177 - David A. Kearney, Gerard Veldman:
Evaluation of network topologies for a run time re-routable network on a programmable chip. 178-185
Runtime Reconfiguration
- Joshua Fender, Jonathan Rose:
A high-speed ray tracing engine built on a field-programmable system. 188-195 - Shyh-Ming Huang, Ing-Jer Huang, Chung-Fu Kao:
Reconfigurable real-time address trace compressor for embedded microprocessors. 196-203 - Andreas Fidjeland, Wayne Luk:
Customising parallelism and caching for machine learning. 204-211
Image Processing
- Stavros Paschalakis, Miroslaw Bober:
A low cost FPGA system for high speed face detection and tracking. 214-221 - Hitoshi Yamada, Takashi Tominaga, Michinori Ichikawa:
An autonomous flying object navigated by real-time optical flow and visual target detection. 222-227 - Manjunath Gangadhar, Dinesh Bhatia:
FPGA based EBCOT architecture for JPEG 2000. 228-233 - Jun Jiang, Wayne Luk, Daniel Rueckert:
FPGA-based computation of free-form deformations in medical image registration. 234-241
Platforms for Reconfigurable Computin
- Hirofumi Sakane, Levent Yakay, Vishal Karna, Clement Leung, Guang R. Gao:
DIMES: an iterative emulation platform for Multiprocessor-System-On-Chip designs. 244-251 - Christian Plessl, Marco Platzner:
TKDM - a reconfigurable co-processor in a PC's memory slot. 252-259
Hardware Compilation and CAD
- Mehrdad Eslami Dehkordi, Stephen Dean Brown:
Performance-driven recursive multi-level clustering. 262-269 - Oskar Mencer, David J. Pearce, Lee W. Howes, Wayne Luk:
Design space exploration with A Stream Compiler. 270-277 - José Gabriel F. Coutinho, Wayne Luk:
Source-directed transformations for hardware compilation. 278-285
Poster Session
- Faycal Bensaali, Abbes Amira, Ahmed Bouridane:
An FPGA based coprocessor for 3D affine transformations. 288-291 - Faycal Bensaali, Abbes Amira, Ahmed Bouridane:
An FPGA based coprocessor for large matrix product implementation. 292-295 - Jen-Wei Hsieh, Guo-Ruey Tsai, Min-Chuan Lin:
Using FPGA to implement a n-channel arbitrary waveform generator with various add-on functions. 296-298 - Yuan-Long Jeang, Liang-Bi Chen, Chia-Pin Huang, Yu-Hsiang Hsu, Ming-Yu Yeh, Kai-Ming Yang:
Design of FPGA-based adaptive remote calibration control system. 299-302 - Xiaofang Wang, Sotirios G. Ziavras:
Performance optimization of an FPGA-based configurable multiprocessor for matrix operations. 303-306 - Han Tao, Toh Lik Khoong, Chai Geok Ling Serena:
Bayesian digital terrain model reconstruction on Virtex-II FPGA. 307-310 - Kazuya Tanigawa, Takashi Kawasaki, Tetsuo Hironaka:
A coarse-grained reconfigurable architecture with low cost configuration data compression mechanism. 311-314 - Yuan-Long Jeang, Liang-Bi Chen, Yi-Ting Chou, Hsin-Chia Su:
An embedded in-circuit emulator generator for SOC platform. 315-318 - Seyed Reza Abdollahi, Seyed Mehdi Fakhraei, Bertan Bakkaloglu, Mahmoud Kamarei:
A crystal-based digital ring oscillator. 319-322 - Peter Yiannacouras, Jonathan Rose:
A parameterized automatic cache generator for FPGAs. 324-327 - Toshinori Sato, Daisuke Morishita:
A field-customizable and runtime-adaptable microarchitecture. 328-331 - Andy Lee, Neil W. Bergmann:
On-chip communication architectures for reconfigurable System-on-Chip. 332-335 - Marco Aurelio Nuño-Maganda, Miguel O. Arias-Estrada, Claudia Feregrino Uribe:
Three video applications using an FPGA based pyramid implementation: Tracking, Mosaics and Stabilization. 336-339 - Neil W. Bergmann, John Williams:
The Egret platform for reconfigurable system on chip. 340-343 - Xue-Jie Zhang, Kam-Wing Ng:
A temporal partitioning approach based on reconfiguration granularity estimation for dynamically reconfigurable systems. 344-347 - Carlos Macián, Sarang Dharmapurikar, John W. Lockwood:
Beyond performance: secure and fair memory management for multiple systems on a chip. 348-351 - Stavros Paschalakis, Peter Lee:
Double precision floating-point arithmetic on FPGAs. 352-358 - Ali Ahmadinia, Christophe Bobda, Jürgen Teich:
Temporal task clustering for online placement on reconfigurable hardware. 359-362 - Noriyuki Aibe, Moritoshi Yasunaga:
Reconfigurable parallel comparation architecture and its application to IP packet filters. 363-366 - Ryosuke Mizuno, Noriyuki Aibe, Moritoshi Yasunaga, Ikuo Yoshihara:
Reconfigurable architecture for probabilistic neural network system. 367-370 - Takeaki Sugimura, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi:
Parallel image processing field programmable gate array for real time image processing system. 372-374 - R. Manjunath, K. S. Gurumurthy:
Artificial neural networks as building blocks of mixed signal FPGA. 375-378 - John Hopf, David A. Kearney:
Specification and integration of software and reconfigurable hardware using Hardware Join Java. 379-382 - Dirk Eilers, Helmut Steckenbiller, Rudi Knorr:
Architecture template with dynamic buffering for runtime reconfiguration of adaptive embedded communication systems. 383-386 - Thomas Lenart, Viktor Öwall, Mats Gustafsson, Mikael Sebesta, Peter Egelberg:
Accelerating signal processing algorithms in digital holography using an FPGA platform. 387-390 - Christophe Bobda, Klaus Danne, Ali Ahmadinia, Jürgen Teich:
A new approach for reconfigurable massively parallel computers. 391-394 - Hala A. Farouk, Magdy Saeb:
An FPGA implementation of a special purpose processor for steganography. 395-398 - John Hopf:
Comparing the bitstreams of applications specified in Hardware Join Java and HandelC. 399-402 - David A. Kearney, Gerard Veldman, David Warren:
Abstractions and primitives enabling runtime resource allocation for dynamic IP cores using virtual platform FPGAs. 403-406 - Mark Jasiunas:
Combined run-time area allocation and long line re-routing for reconfigurable computing. 407-410 - David A. Kearney, Gerard Veldman:
A concurrent multi-bank memory arbiter for dynamic IP cores using idle skip round robin. 411-414 - Hamid Reza Ghasemi, Hossein Mohammadi, Behnam Robatmili, Nasser Yazdani:
Augmenting general purpose processors for network processing. 416-419 - Chee Wei Liang, Noohul Basheer Zain Ali, Ramesh Seth Nair:
Design of low cost FPGA based PCI Bus Sniffer. 420-423 - Hongtu Jiang, Viktor Öwall:
FPGA implementation of real-time image convolutions with three level of memory hierarchy. 424-427 - Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Alireza Ejlali:
Fault injection into SRAM-based FPGAs for the analysis of SEU effects. 428-430 - Zhiguo Ge, Jirong Liao, Weng-Fai Wong:
Compiling to FPGAs via an EPIC compiler's intermediate representation. 431-434 - Jeffrey J. Cook, Lee Baugh, Derek B. Gottlieb, Nicholas P. Carter:
Mapping computation kernels to clustered programmable-reconfigurable processors. 435-438 - Yongxiang Hu, Yang Cai, Mark Tomzak, Tsengdar Lee:
Multisensor inversion with high-performance FPGA computation. 439-442 - Esam El-Araby, Mohamed Taher, Kris Gaj, Tarek A. El-Ghazawi, David Caliga, Nikitas A. Alexandridis:
Exploiting system-level parallelism in the application development on a reconfigurable computer. 443-446 - Alex Carreira, Trevor W. Fox:
The Multiplier Tree FIR filter architecture. 447-450 - Anant Utgikar, Guna Seetharaman, Ha Vu Le:
FPGA implementable architecture for geometric global positioning. 451-455
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