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ORCID9. Great Lakes Symposium on VLSI 1999: Ann Arbor, MI, USA
- 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA. IEEE Computer Society 1999, ISBN 0-7695-0104-4
Testing
- Irith Pomeranz, Sudhakar M. Reddy:
PASTA: Partial Scan to Enhance Test Compaction. 4-7 - Paulo F. Flores, Horácio C. Neto, João P. Marques Silva:
On Applying Set Covering Models to Test Set Compaction. 8-11 - Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara:
On Test Generation with A Limited Number of Tests. 12-15 - Spyros Tragoudas, Maria K. Michael:
Functional ATPG for Delay Faults. 16-19 - Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis:
On Path Delay Fault Testing of Multiplexer - Based Shifters. 20-23 - Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. 24-
VLSI Design 1
- Aamir A. Farooqui, Vojin G. Oklobdzija:
VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing. 30-33 - Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin:
The Design of a Register Renaming Unit. 34-37 - Oliver Hauck, M. Garg, Sorin A. Huss:
Efficient and Safe Asynchronous Wave-Pipeline Architectures for Datapath and Control Unit Applications. 38-41 - Jörg Hilgenstock, Klaus Herrmann, Peter Pirsch:
Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM. 42-45 - Janardhan H. Satyanarayana, Keshab K. Parhi:
Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation. 46-49 - Yung-Hsiang Lu, Giovanni De Micheli:
Adaptive Hard Disk Power Management on Personal Computers. 50-
Delay Modeling
- Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Inductance Effects in RLC Trees. 56-59 - Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi:
S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric. 60-63 - Yanhong Yuan, Prithviraj Banerjee:
ICE: Incremental 3-Dimensional Capacitance and Resistance Extraction for an Iterative Design Environment. 64-67 - Ninglong Lu, Ibrahim N. Hajj:
An Exact Analytical Time-Domain Model Of Distributed RC Interconnects for High Speed Nonlinear Circuit Applications. 68-
VLSI Design 2
- Gianluca Cornetta
, Jordi Cortadella:
A Radix-16 SRT Division Unit with Speculation of the Quotient Digits. 74-77 - Louis Luh, John Choma Jr., Jeffrey T. Draper:
Area-Efficient Area Pad Design for High Pin-Count Chips. 78-81 - Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni:
New 2 Gbit/s CMOS I/O pads. 82-85 - Jörg Henkel:
A Methodology for Minimizing Power Dissipation of Embedded Systems through Hardware/Software Partitioning. 86-
Analog and Digital Testing
- Anna Maria Brosa, Joan Figueras:
On Optimizing Test Strategies for Analog Cells. 92-96 - Erik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, Victor Boyadzhyan, Brent R. Blaes, Wai-Chi Fang:
Novel Design for Testability of a Mixed-Signal VLSI IC. 97-100 - Ying Wang, Han Ngee Tan:
The Development of Analog SPICE Behavioral Model Based on IBIS Model. 101- - Mostafa I. H. Abd-El-Barr, Yanging Xu, Carl McCrosky:
Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits. 388- - Von-Kyoung Kim, Tom Chen, Mick Tegethoff:
Fault Coverage Estimation for Early Stage of VLSI Design. 105-108 - Bassam Shaer, Sami A. Al-Arian, David L. Landis:
Pseudo-Exhaustive Testing of Sequential Circuits. 109-
Nanoelectronics 1
- James C. Ellenbogen:
Advances Toward Molecular-Scale Electronic Digital Logic Circuits: A Review and Prospectus. 392- - David B. Janes, Ronald P. Andres, E. H. Chen, J. Dicke, V. R. Kolagunta, Jochen P. Lauterbach, Takhee Lee, Jia Liu, M. R. Melloch, E. L. Peckham, T. Pletcher, Ron Reifenberger, H. J. Ueng, B. L. Walsh, J. M. Woodall, C. P. Kubiak, B. Kasibhatla:
Self-Assembly Based Approaches for Metal/Molecule/Semiconductor Nanoelectronic Circuits. 114-117 - Michael T. Niemier, Peter M. Kogge:
Logic in Wire: Using Quantum Dots to Implement a Microprocessor. 118-121 - Árpád Csurgay, Craig S. Lent, Wolfgang Porod:
Why is Time-Varying Control Necessary for Signal Processing with Locally-Connected Quantum-Dot Arrays? 122- - Stephen Marshall Goodnick, Jonathan P. Bird, David K. Ferry, Allen D. Gunther, Maroun D. Khoury, Michael N. Kozicki, M. J. Rack, Trevor J. Thornton, D. Vasileska-Kafedezka:
Transport in Split Gate MOS Quantum Dot Structures. 394- - Tom P. E. Broekaert, Berinder Brar, Frank J. Morris, Alan C. Seabaugh, Gary A. Frazier:
Resonant Tunneling Technology for Mixed Signal and Digital Circuits in the 10-100 GHz Domain. 123-
Synthesis
- Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Sharon Hu:
Efficient Algorithms for Finding Highly Acceptable Designs Based on Module-Utility Selections. 128-131 - Ronnie L. Wright, Michael A. Shanblatt:
Reducing BDD Size by Exploiting Structural Connectivity. 132-135 - Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya:
An Integrated Approach for Synthesizing LUT Networks. 136-139 - Abhijit Ghosh, Sandeep K. Lodha, Ranga Vemuri:
Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops. 140-143 - Rohit Sharma, C. P. Ravikumar:
Design Issues in Synthesis of Reusable Cores. 144-
Nanoelectronics 2
- Masafumi Yamamoto, Hideaki Matsuzaki, Toshihiro Itoh, Takao Waho, T. Akeyoshi, J. Osaka:
Ultrahigh-Speed Circuits Using Resonant Tunneling Devices. 150-153 - Hideaki Matsuzaki, Toshihiro Itoh, Masafumi Yamamoto:
A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs. 154-157 - Tetsuya Uemura, Pinaki Mazumder:
Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit. 158-161 - Patrick Fay, Gary H. Bernstein, David H. Chow, Joel N. Schulman, Pinaki Mazumder, William Williamson III, Barry K. Gilbert:
Integration of InAs/AlSb/GaSb Resonant Interband Tunneling Diodes with Heterostructure Field-Effect Transistors for Ultra-High-Speed Digital Circuit Applications. 162-165 - Daniel Berzon, Terry J. Fountain:
A Memory Design in QCAs using the SQUARES Formalism. 166-
Design Issues
- Chia-Pin R. Liu, Jacob A. Abraham:
Transistor Level Synthesis for Static CMOS Combinational Circuits. 172-175 - Carlos Humberto Llanos Quintero, Marius Strum:
SINMEF - A Decomposition Based Synthesis Tool for Large FSMs. 176-179 - Weiwei Li, Zhongwei Xu, Yan Jin:
An Approach for Testing Safety-Critical Software. 180-183 - Travis E. Doom, Anthony S. Wojcik, Moon-Jung Chung:
Design Recovery for Incomplete Combinational Logic. 184-187 - Alberto Macii, Enrico Macii, Giuseppe Odasso, Massimo Poncino, Riccardo Scarsi:
Regression-Based Macromodeling for Delay Estimation of Behavioral Components. 188-191 - Stephen A. Blythe, Robert A. Walker:
Efficiently Searching the Optimal Design Space. 192-
VLSI Circuits 1
- Yiu Wu, John Ling, Ward J. Helms:
A Bandpass Sigma-Delta for Software Low-Power and Low-Voltage Radio by Using PATH Technique. 198-201 - Seung-Moon Yoo, Sung-Mo Kang:
No-Race Charge-Recycling Differential Logic (NCDL). 202-205 - Tuna B. Tarim, Mohammed Ismail:
Linear Transconductors Using Low Voltage Low Power Square-Law Cmos Cells. 206-209 - Victor Varshavsky, Masayuki Tsukisaka:
Current Sensor on the Base of Permanent Pre-chargeable Amplifier. 210-213 - Navindra Yadav, Michael J. Schulte, John Glossner:
Parallel Saturating Fractional Arithmetic Units. 214-217 - Shugang Wei, Kensuke Shimizu:
Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation. 218-
Short Papers 1
- H.-Ch. Dahmen, Uwe Gläser, Zoran Stamenkovic:
Modell Evaluation Using Genetic Manipulation Techniques. 224-225 - Khaled M. Elleithy, E. G. Abd-El-Fattah:
A Genetic Algorithm for Register Allocation. 226-227 - Kanad Chakraborty, Natesan Venkateswaran:
Congestion Mitigation During Placement. 228-229 - John Karro, James P. Cohoon:
A Spiffy Tool for the Simultaneous Placement and Global Routing for Three-Dimensional Field-Programmable Gate Arrays. 230-231 - Sae Hwan Kim, Shiu-Kai Chin:
Formal Verification of Tree-Structured Carry-Lookahead Adders. 232-233 - Samit Chaudhuri, Robert A. Walker:
Bounding Algorithms for Design Space Exploration. 234-235 - Hoda S. Abdel-Aty-Zohdy, Mahmoud Al-Nsour:
Digital Neural Processing Unit for Electronic Nose. 236-237 - Xiaohui Wang, Wolfgang Porod:
A Low Power Charge-Recycling CMOS Clock Buffer. 238-239 - Richard F. Hobson, Allan R. Dyck:
A Multiple-Input Single-Phase Clock Flip-Flop Family. 240-241 - Igor Lemberski:
Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs. 242-243 - Md. Altaf-Ul-Amin, Zahari Mohamed Darus:
VHDL Design of a Test Processor Based on Mixed-Mode Test Generation. 244-
Physical Design
- Jim E. Crenshaw, Majid Sarrafzadeh, Prithviraj Banerjee, Pradeep Prabhakaran:
An Incremental Floorplanner. 248-251 - R. Balakrishnan, Richard F. Hobson:
A Greedy Router with Technology Targetable Output. 252-255 - Wei Li, Dilip K. Banerji:
Routability Prediction for Hierarchical FPGAs. 256-259 - Daniel Chillet, Olivier Sentieys, Michel Corazza:
Memory Unit Design for Real Time DSP Applications. 260-
MEMS
- Dennis Gibson, Carla N. Purdy, Alva Hare, Fred R. Beyette Jr.:
Design Automation of MEMS Systems Using Behavioral Modeling. 266-269 - Robert L. Ewing:
Blending Symbolic Matrix and Dimensional Numerical Simulation Methodology for Mechatronics Systems. 270-273 - N. Tayebi, A. K. Tayebi, Y. Belkacemi:
Numerical Tools for Fracture of MEMS Devices. 274-
Verification
- Dinos Moundanos, Jacob A. Abraham:
Formal Checking of Properties in Complex Systems Using Abstractions. 280-283 - Subhashini Balakrishnan, Sofiène Tahar:
A Hierarchical Approach to the Formal Verification of Embedded Systems Using MDGs. 284-287 - Stefan Hendricx, Luc J. M. Claesen:
Symbolic Multi-Level Verification of Refinement. 288-291 - Ilya Levin, Vladimir Sinelnikov:
Self-Checking of FPGA-Based Control Units. 292-295 - Yi Yu, Fangmei Wu:
A Software Acceptance Testing Technique Based on Knowledge Accumulation. 296-299 - Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal:
A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability. 300-
VLSI Circuits 2
- Amr N. Hafez, Mohamed I. Elmasry:
A Novel Low Power Low Phase-Noise PLL Architecture for Wireless Transceivers. 306-309 - Chulwoo Kim, Seung-Moon Yoo, Sung-Mo Kang:
NMOS Energy Recovery Logic. 310-313 - Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman:
Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems. 314-317 - Lim Chu Aun, S. M. Rezaul Hasan:
An all Digital BiCMOS Phase Lock Loop for VLSI Processors. 318-320 - José Francisco López, Roberto Sarmiento, Antonio Núñez, Kamran Eshraghian, Stefan Lachowicz, Derek Abbott:
Low Power Techniques for Digital GaAs VLSI. 321-324 - Amr G. Wassal, M. Anwarul Hasan:
A VLSI Architecture for ATM Algorithm-Agile Encryption. 325-
Short Papers 2
- Dirk Stroobandt:
On an Efficient Method for Estimating the Interconnection Complexity of Designs and on the Existence of Region III in Rent's Rule. 330-331 - Erik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, Victor Boyadzhyan, Brent R. Blaes, Wai-Chi Fang:
Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS. 332-333 - S. Gailhard, Nathalie Julien, Adel Baganne, Eric Martin:
Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures. 334-335 - Ihn Kim, Craig S. Steele, Jefferey G. Koller:
A Fully Pipelined, 700MBytes/s DES Encryption Core. 386- - Teruhiko Kamigata, Koso Murakami, Makoto Iwata, Hiroaki Terada:
Proposal of Data-Driven Processor Architecture Qv-K1. 336-337 - Srinivas Katkoori, Ranga Vemuri:
Accurate Resource Estimation Algorithms for Behavioral Synthesis. 338-339 - Von-Kyoung Kim, Tom Chen:
Assessing Defect Coverage of Memory Testing Algorithms. 340- - Jacob Savir:
Memory Chip BIST Architecture. 384- - Xiaowei Li, Paul Y. S. Cheung:
Exploiting Test Resource Optimization in Data Path Synthesis for BIST. 342-343 - Christian Pacha, Peter Glösekötter, Karl Goser, Uwe Auer, Werner Prost, Franz-Josef Tegude:
Resonant Tunneling Transistors for Threshold Logic Circuit Applications. 344-345 - David Crawley:
A Multilevel Cache Memory Architecture for Nanoelectronics. 346-
Low Power
- Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
ALPS: A Peak Power Estimation Tool for Sequential Circuits. 350-353 - Roberto Corgnati, Enrico Macii, Massimo Poncino:
Clustered Table-Based Macromodels for RTL Power Estimation. 354-357 - Yuyu Chang, John Choma Jr., Jack Wills:
The Design of Cmos Gigahertz-Band Continuous-Time Active Lowpass Filters with Q-Enhancement Circuits. 358-361 - Yuke Wang, Xiaoyu Song, El Mostapha Aboulhamid:
A New Algorithm for RNS Magnitude Comparison Based on New Chinese Remainder Theorem II. 362-
VLSI Circuits 3
- Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada:
Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method. 368-371 - Chi-Hung Lin, Mohammed Ismail:
A 1.8V High Dynamic-Range CMOS High-Speed Four Quadrant Multiplier. 372-375 - Xiaopeng Li, Mohammed Ismail:
A Second-Order Sigma-Delta Modulator with Built-in VGA to Improve SNR and Harmonic Distortion. 376-379 - R. Shalem, Lizy Kurian John, Eugene John:
A Novel Low Power Energy Recovery Full Adder Cell. 380-
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