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ORCIDHLDVT 2001: Monterey, California, USA
- Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, Monterey, California, USA, November 7-9, 2001. IEEE Computer Society 2001, ISBN 0-7695-1411-1
Design Validation of Microprocessors
- Noppanunt Utamaphethai, Ronald D. Blanton, John Paul Shen:
Relating buffer-oriented microarchitecture validation to high-level pipeline functionality. 3-8 - Prabhat Mishra, Nikil D. Dutt
, Alex Nicolau:
Automatic validation of pipeline specifications. 9-13 - Nabarun Bhattacharyya, A. Wang:
Automatic test generation for micro-architectural verification of configurable microprocessor cores with user extensions. 14-15
Techniques for High Level Design Validation and Test
- Michael D. McKinney:
Integrating Perl, Tcl and C++ into simulation-based ASIC verification environments. 19-24 - Kiyoharu Hamaguchi:
Symbolic simulation heuristics for high-level design descriptions with uninterpreted functions. 25-30 - Irith Pomeranz, Sudhakar M. Reddy:
Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description. 31-35
Invited Session: State-of-the-Art Formal Verification Techniques
- Michael S. Hsiao, Jawahar Jain:
Practical use of sequential ATPG for model checking: going the extra mile does pay off. 39-44 - Claudia Blank, Hans Eveking, Jens Levihn, Gerd Ritter:
Symbolic simulation techniques-state-of-the-art and applications. 45-50
Short Papers: High Level Verification and Analysis
- Sandeep K. Shukla, Rajesh K. Gupta:
A model checking approach to evaluating system level dynamic power management policies for embedded systems. 53-57 - Byeong Min, Gwan Choi:
RTL functional verification using excitation and observation coverage. 58-63 - Allon Adir, Eitan Marcus, Michal Rimon, Amir Voskoboynik:
Improving test quality through resource reallocation. 64-69 - Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre:
Taylor expansion diagrams: a new representation for RTL verification. 70-75
Short papers: High Level Timing Verification and Testing
- Sungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, Ahmed Amine Jerraya:
Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication. 79-82 - Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris:
Test pattern generation for timing-induced functional errors in hardware-software systems. 83-88 - Marek Jersak, Kai Richter, Rolf Ernst:
Combining complex event models and timing constraints. 89-94 - Annette Bunker, Ganesh Gopalakrishnan:
Using live sequence charts for hardware protocol specification and compliance verification. 95-100
Verification of Real Life Designs
- Tim Braun, Anne Condon, Alan J. Hu, Kai S. Juse, Marius Laza, Michael Leslie, Rita Sharma:
Proving sequential consistency by model checking. 103-108 - Shuvendu K. Lahiri, Carl Pixley, Ken Albin:
Experience with term level modeling and verification of the M*CORE TM microprocessor core. 109-114 - Roope Kaivola, Naren Narasimhan:
Formal verification of the Pentium(R) 4 multiplier. 115-120
High-Level Specification and Verification
- Peer Johannsen:
Reducing bitvector satisfiability problems to scale down design sizes for RTL property checking. 123-128 - Felice Balarin, Jerry R. Burch, Luciano Lavagno, Yosinori Watanabe, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli:
Constraints specification at higher levels of abstraction. 129-133 - Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir:
A language formalism for verification of PowerPCTM custom memories using compositions of abstract specifications. 134-141
High-Level Test Generation and Coverage Analysis
- Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model. 145-150 - Ian G. Harris:
Hardware-software covalidation: fault models and test generation. 151-156 - Farzan Fallah, Indradeep Ghosh:
Observability enhanced coverage analysis of C programs for functional validation. 157-162
Improved Techniques for Boolean Reasoning
- Dong Wang, Edmund M. Clarke, Yunshan Zhu, James H. Kukula:
Using cutwidth to improve symbolic simulation and Boolean satisfiability. 165-170 - Zurab Khasidashvili, John Moondanos, Daher Kaiss, Ziyad Hanna:
An enhanced cut-points algorithm in formal equivalence verification. 171-176 - Ganapathy Parthasarathy, Chung-Yang Huang, Kwang-Ting Cheng:
An analysis of ATPG and SAT algorithms for formal verification. 177-182
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