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ORCIDHLDVT 2002: Cannes, France
- Seventh IEEE International High-Level Design Validation and Test Workshop 2002, Cannes, France, October 27-29, 2002. IEEE Computer Society 2002, ISBN 0-7803-7655-2
High Level Design Validation
- David A. Sigüenza-Tortosa, Jari Nurmi
:
VHDL-based simulation environment for Proteo NoC. 1-6 - Astrit Ademaj:
Slightly-off-specification failures in the time-triggered architecture. 7-12 - Priyank Kalla, Maciej J. Ciesielski, Emmanuel Boutillon, Eric Martin:
High-level design verification using Taylor Expansion Diagrams: first results. 13-17 - A. Castelnuovo, Andrea Fedeli, Alessandro Fin, Franco Fummi, Graziano Pravadelli, Umberto Rossi, F. Sforza, Franco Toto:
A 1000X speed up for properties completeness evaluation. 18-22 - Axel G. Braun, Joachim Gerlach, Wolfgang Rosenstiel:
Checking temporal properties in SystemC specifications. 23-27
Invited Special Session: Challenges for Debug and Validation
- Bob Bentley:
High level validation of next-generation microprocessors. 31-35 - Gérard Berry, Lionel Blanc, Amar Bouali, Jerome Dormoy:
Top-level validation of system-on-chip in Esterel Studio. 36-41 - Klaus-Dieter Schubert:
Practical experiences in functional simulation. An integrated method from unit to co-simulation. 42-44
Golbal System Validation
- Gethin Norman, David Parker, Marta Z. Kwiatkowska, Sandeep K. Shukla, Rajesh K. Gupta:
Formal analysis and validation of continuous-time Markov chain based system level power management strategies. 45-50 - Iuliana Bacivarov, Sungjoo Yoo, Ahmed Amine Jerraya:
Timed HW-SW cosimulation using native execution of OS and application SW. 51-56 - Idriz Smaili, Astrit Ademaj:
Setting break-points in distributed time-triggered architecture. 57-62 - Matteo Sonza Reorda, Massimo Violante, Nicola Mazzocca, Salvatore Venticinque, Andrea Bobbio, Giuliana Franceschinis:
A hierarchical approach for designing dependable systems. 63-68 - Mohammad Reza Mousavi, Giovanni Russello, Michel R. V. Chaudron, Michel A. Reniers, Twan Basten, Angelo Corsaro, Sandeep K. Shukla, Rajesh K. Gupta, Douglas C. Schmidt:
Using Aspect-GAMMA in the design of embedded systems. 69-74
Validation of Processors
- Allon Adir, Gil Shurek:
Generating concurrent test-programs with collisions for multi-processor verification. 77-82 - Allon Adir, Roy Emek, Eitan Marcus:
Adaptive test program generation: planning for the unplanned. 83-88 - John Dielissen, Benito Otero Mathijssen, Jos Huisken:
Breaking an application specific instruction-set processor: the first step towards embedded software testing. 89-92 - David Malandain, Pim Palmen, Matthew Taylor, Merav Aharoni, Yaron Arbetman:
An effective and flexible approach to functional verification of processor families. 93-98 - Prabhat Mishra, Nikil D. Dutt:
Automatic functional test program generation for pipelined processors using model checking. 99-103
Formal Verification Methods
- Ranan Fraer, Shahid Ikram, Gila Kamhi, Tim Leonard, Abdel Mokkedem:
Accelerated verification of RTL assertions based on satisfiability solvers. 107-110 - Amnon Rosenmann, Ziyad Hanna:
Alignability equivalence of synchronous sequential circuits. 111-114 - Zurab Khasidashvili, John Moondanos, Ziyad Hanna:
TRANS: efficient sequential verification of loop-free circuits. 115-120 - H. N. Nguyen, P. Koumou, Bernard Candaele, Michel Sarlotte, Christian Antoine, S. Emeriau:
Verification of a DSP IP cores by model checking. 121-124 - Xi Chen, Fang Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Formal verification of embedded system designs at multiple levels of abstraction. 125-130
RTL Verification and Validation
- César A. M. Marcon, Fabiano Hessel, Alexandre M. Amory, Luis H. L. Ries, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Prototyping of embedded digital systems from SDL language: a case study. 133-138 - Hiroshi Saito, Takaya Ogawa, Thanyapat Sakunkonchak, Masahiro Fujita, Takashi Nanya:
An equivalence checking methodology for hardware oriented C-based specifications. 139-144 - Roy Emek, Itai Jaeger, Yehuda Naveh, Gadi Bergman, Guy Aloni, Yoav Katz, Monica Farkash, Igor Dozoretz, Alex Goldin:
X-Gen: a random test-case generator for systems and SoCs. 145-150 - Alex Wakefield, Bassam Jamil Mohd:
Constructing reusable testbenches. 151-155 - Markus Wannemacher, Mihai Munteanu, Sacha Perret, Rolf Singer:
Taking the best out of two worlds: prototyping and hardware emulation. 156-161
Design for Testability and Test
- Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre:
A simple and effective compression scheme for test pins reduction. 165-168 - Gert Jervan, Zebo Peng, Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante:
High-level and hierarchical test sequence generation. 169-174 - Fei Xin, Ian G. Harris:
Test generation for hardware-software covalidation using non-linear programming. 175-180 - Piotr Gawkowski, Janusz Sosnowski:
Experimental validation of fault detection and fault tolerance mechanisms. 181-186
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