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ORCID18th HPCA 2012: New Orleans, LA, USA
- 18th IEEE International Symposium on High Performance Computer Architecture, HPCA 2012, New Orleans, LA, USA, 25-29 February, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-0827-4
Reliability
- Jinho Suh, Murali Annavaram
, Michel Dubois:
MACAU: A Markov model for reliability evaluations of caches under Single-bit and Multi-bit Upsets. 3-14 - Manu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Bipin Rajendran, Rajeev Balasubramonian, Viji Srinivasan:
Efficient scrub mechanisms for error-prone emerging memories. 15-26 - Timothy N. Miller, Xiang Pan, Renji Thomas, Naser Sedaghati, Radu Teodorescu:
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips. 27-38
Memory Systems I
- Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads. 41-52 - Min Kyu Jeong, Doe Hyun Yoon, Dam Sunwoo, Michael B. Sullivan, Ikhwan Lee, Mattan Erez:
Balancing DRAM locality and parallelism in shared memory CMP systems. 53-64 - Janani Mukundan, José F. Martínez:
MORSE: Multi-objective reconfigurable self-optimizing memory scheduler. 65-76
Heterogenous Architectures
- Jacob Adriaens, Katherine Compton, Nam Sung Kim, Michael J. Schulte:
The case for GPGPU spatial multitasking. 79-90 - Jaekyu Lee, Hyesoon Kim:
TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture. 91-102 - Yi Yang, Ping Xiang, Mike Mantor, Huiyang Zhou:
CPU-assisted GPGPU on fused CPU-GPU architectures. 103-114 - Jesse Benson, Ryan Cofell, Chris Frericks, Chen-Han Ho, Venkatraman Govindaraju, Tony Nowatzki, Karthikeyan Sankaralingam:
Design, integration and implementation of the DySER hardware accelerator into OpenSPARC. 115-126
Parallel Architectures
- Daniel Sánchez, Christos Kozyrakis:
SCD: A scalable coherence directory with flexible sharer set encoding. 129-140 - Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström:
π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. 141-152 - Xuehai Qian, Benjamín Sahelices, Josep Torrellas:
BulkSMT: Designing SMT processors for atomic-block execution. 153-164 - Sheng Ma, Natalie D. Enright Jerger, Zhiying Wang:
Supporting efficient collective communication in NoCs. 165-176
Memory Systems and I/O
- Yangyang Pan, Guiqiang Dong, Qi Wu, Tong Zhang:
Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications. 179-188 - Kevin T. Lim, Yoshio Turner, Jose Renato Santos, Alvin AuYoung, Jichuan Chang, Parthasarathy Ranganathan, Thomas F. Wenisch:
System-level implications of disaggregated memory. 189-200 - Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang, Bruce R. Childers:
Improving write operations in MLC phase change memory. 201-210
Caches
- Dyer Rolán, Basilio B. Fraguela, Ramon Doallo:
Adaptive Set-Granular Cooperative Caching. 213-224 - David Daly, Harold W. Cain:
Cache restoration for highly partitioned virtualized systems. 225-234 - Samira Manabi Khan, Zhe Wang, Daniel A. Jiménez:
Decoupled dynamic cache segmentation. 235-246
Best Paper Session
- Arun Raghavan, Yixin Luo, Anuj Chandawalla, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin:
Computational sprinting. 249-260 - John Sartori, Ben Ahrens, Rakesh Kumar:
Power balanced pipelines. 261-272 - Steven J. Battle, Andrew D. Hilton, Mark Hempstead, Amir Roth:
Flexible register management using reference counting. 273-284
Power and Energy
- Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Minyi Guo, Xiaoyao Liang:
AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture. 287-298 - Raid Zuhair Ayoub, Rajib Nath, Tajana Rosing:
JETC: Joint energy thermal and cooling management for memory and CPU subsystems in servers. 299-310 - Karthik T. Sundararajan, Vasileios Porpodas, Timothy M. Jones, Nigel P. Topham, Björn Franke:
Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs. 311-322 - Houman Homayoun, Vasileios Kontorinis, Amirali Shayan, Ta-Wei Lin, Dean M. Tullsen:
Dynamically heterogeneous cores through 3D resource pooling. 323-334
Parallel Programming and Architectures
- Cedomir Segulja, Tarek S. Abdelrahman:
Architectural support for synchronization-free deterministic parallel programming. 337-348 - Shanxiang Qi, Norimasa Otsuki, Lois Orosa Nogueira, Abdullah Muzahid, Josep Torrellas:
Pacman: Tolerating asymmetric data races with unintrusive hardware. 349-360 - Yuelu Duan, Xing Zhou, Wonsun Ahn, Josep Torrellas:
BulkCompactor: Optimized deterministic execution via Conflict-Aware commit of atomic blocks. 361-372 - Dan Lin, Nigel Medforth, Kenneth S. Herdy, Arrvindh Shriraman, Robert D. Cameron:
Parabix: Boosting the efficiency of text processing on commodity processors. 373-384
Performance Modeling
- Ganesh Balakrishnan, Yan Solihin:
WEST: Cloning data cache behavior using Stochastic Traces. 387-398 - Tianshi Chen, Yunji Chen, Qi Guo, Olivier Temam, Yue Wu, Weiwu Hu:
Statistical performance comparisons of computers. 399-410
Industrial Track
- Valentina Salapura, Tejas Karkhanis, Priya Nagpurkar, José E. Moreira:
Accelerating business analytics applications. 413-422 - Augusto Vega, Pradip Bose, Alper Buyuktosunoglu, Jeff H. Derby, Michele Franceschini, Charles Johnson, Robert K. Montoye:
Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor. 423-432 - Nagabhushan Chitlur, Ganapati Srinivasa, Scott Hahn, P. K. Gupta, Dheeraj Reddy, David A. Koufaty, Paul Brett, Abirami Prabhakaran, Li Zhao, Nelson Ijih, Suchit Subhaschandra, Sabina Grover, Xiaowei Jiang, Ravi R. Iyer:
QuickIA: Exploring heterogeneous architectures on real prototypes. 433-440
NoC
- Nan Jiang, Daniel U. Becker, George Michelogiannakis, William J. Dally:
Network congestion avoidance through Speculative Reservation. 443-454 - Jung Ho Ahn, Sungwoo Choo, John Kim:
Network within a network approach to create a scalable high-radix router microarchitecture. 455-466 - Sheng Ma, Natalie D. Enright Jerger, Zhiying Wang:
Whole packet forwarding: Efficient design of fully adaptive routing algorithms for networks-on-chip. 467-478
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