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ORCIDICCAD 1990: Santa Clara, California, USA
- IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical Papers. IEEE Computer Society 1990, ISBN 0-8186-2055-2
Session 1A: Routing Algorithms and Complexity 1
- Peter Koo, Fabrizio Lombardi, Donatella Sciuto:
A Routing Algorithm for Harvesting Multipipeline Arrays with Small Intercell and Pipeline Delays. 2-5 - Shinichiro Haruyama, D. F. Wong
, Donald S. Fussell:
Topological Routing Using Geometric Information. 6-9 - Yang Cai, D. F. Wong:
An Optimal Channel Pin Assignment Algorithm. 10-13
Session 1B: Timing Analysis and Verification
- Joel Grodstein, Jengwei Pan, William J. Grundmann, Bruce Gieseke, Yao-Tsung Yen:
Constraint Identification for Timing Verification. 16-19 - Joel Grodstein, Jim Montanaro, Susanne Marino:
Race Detection for Two-Phase Systems. 20-23 - Habib Youssef, Eugene Shragowitz:
Timing Constraints for Correct Performance. 24-27
Session 1C: Verification
- Srinivas Devadas, Kurt Keutzer:
An Automata-Theoretic Approach to Behavioral Equivalence. 30-33 - Eduard Cerny, C. Mauras:
Tautology Checking Using Cross-Controllability and Cross-Observability Relations. 34-37 - Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda:
Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. 38-41
Session 2A: Routing Methods
- G. Meixner, Ulrich Lauther:
A New Global Router Based on a Flow Model and Linear Assignment. 44-47 - Somchai Prasitjutrakul, William J. Kubitz:
A Timing-Driven Global Router for Custom Chip Design. 48-51 - Wayne Wei-Ming Dai, Raymond Kong, Jeffrey Jue:
Rubber Band Routing and Dynamic Data Representation. 52-55 - Kaoru Kawamura, Tatsuya Shindo, Toshiyuki Shibuya, Hideki Miwatari, Yoshie Ohki:
Touch and Cross Router. 56-59
Session 2B: Performance Enhancements for Logic and Switch-Level Simulation
- Rahul Razdan, Gabriel P. Bischoff, Ernst G. Ulrich:
Exploitation of Periodicity in Logic Simulation of Synchronous Circuits. 62-65 - David T. Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham:
SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. 66-69 - Peter M. Maurer:
Optimization of the Parallel Technique for Compiled Unit-Delay Simulation. 70-73 - Evstratios Vandris, Gerald E. Sobelman:
Fast Switch-Level Fault Simulation Using Functional Fault Modeling. 74-77
Session 2C: Interacting Sequential Machines and Boolean Function Manipulation
- Wayne H. Wolf:
An Algorithm for Nearly-Minimal Collapsing of Finite-State Machine Networks. 80-83 - Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. 84-87 - Bill Lin, Fabio Somenzi:
Minimization of Symbolic Relations. 88-91 - Arvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton:
Algorithms for Discrete Function Manipulation. 92-95
Session 3A: Floorplanning Algorithms
- Massoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh:
Floorplanning with Pin Assignment. 98-101 - Chong-Min Kyung, Peter V. Kraus, Dieter A. Mlynski:
Diffusion - An Analytic Procedure Applied to Macro Cell Placement. 102-105 - Gopalakrishnan Vijayan, Ren-Song Tsay:
Floorplanning by Topological Constraint Reduction. 106-109
Session 3B: Yield Maximization
- M. A. Styblinski:
Design for Circuit Quality: Yield Maximization, Minimax, and Taguchi Approach. 112-115 - Linda Milor, Alberto L. Sangiovanni-Vincentelli:
Computing Parametric Yield Accurately and Efficiently. 116-119 - Peter Feldmann, Stephen W. Director:
Accurate and Efficient Evaluation of Circuit Yield and Yield Gradients. 120-123
Session 3C: Sequential Verification
- Olivier Coudert, Jean Christophe Madre:
A Unified Framework for the Formal Verification of Sequential Circuits. 126-129 - Hervé J. Touati, Hamid Savoj, Bill Lin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Implicit State Enumeration of Finite State Machines Using BDDs. 130-133 - Hyunwoo Cho, Gary D. Hachtel, Seh-Woong Jeong, Bernard Plessier, Eric M. Schwarz, Fabio Somenzi:
ATPG Aspects of FSM Verification. 134-137
Session 4A: Floorplanning Systems
- Masako Murofushi, Masaaki Yamada, Takashi Mitsuhashi:
FOLM-Planner: A New Floorplanner with a Frame Overlapping Floorplan Model Suitable for SOG (Sea-of-Gates) Type Gate Arrays. 140-143 - Allen C.-H. Wu, Daniel Gajski:
Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists. 144-147 - Thomas Lengauer, Rolf Müller:
A Robust Framework for Hierarchical Floorplanning with Integrated Global Wiring. 148-151 - Alexander Herrigel:
GRCA: A Global Approach for Floorplanning Synthesis in VLSI Macrocell Design. 152-155
Session 4B: Circuit Simulation
- Yun-Cheng Ju, Fred L. Yang, Resve A. Saleh:
Mixed-Mode Incremental Simulation and Concurrent Fault Simulation. 158-161 - Chandramouli Visweswariah, Peter Feldmann, Ronald A. Rohrer:
Incorporation of Inductors in Piecewise Approximate Circuit Simulation. 162-165 - Rui Wang, Omar Wing:
Analysis of VLSI Microconductor Systems by Bi-Level Waveform Relaxation. 166-169 - Charles A. Zukowski, George Gristede, Albert E. Ruehli:
Measuring Error Propagation in Waveform Relaxation Algorithms. 170-173
Session 4C: Logic Synthesis
- M. Ohmura, Hiroto Yasuura, Keikichi Tamaru:
Extraction of Functional Information from Combinatorial Circuits. 176-179 - Se-Kyoung Hong, In-Cheol Park, Chong-Min Kyung:
An O(n3logn)-Heuristic for Microcode Bit Optimization. 180-183 - Peter Vanbekbergen, Francky Catthoor, Gert Goossens, Hugo De Man:
Optimized Synthesis of Asynchronous Control Circuits from Graph-Theoretic Specifications. 184-187 - David E. Wallace, Mandalagiri S. Chandrasekhar:
High-Level Delay Estimation for Technology-Independent Logic Equations. 188-191
Session 5A: Analog Layout
- Yoichi Shiraishi, Mitsuyuki Kimura, Kazuhiko Kobayashi, Tetsuro Hino, Miki Seriuchi, Manabu Kusaoke:
A High-Packing Density Module Generator for Bipolar Analog LSIs. 194-197 - Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli:
Constraint-Based Channel Routing for Analog and Mixed Analog/Digital Circuits. 198-201 - Enrico Malavasi, Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli:
A Routing Methodology for Analog Integrated Circuits. 202-205
Session 5B: High-Level Synthesis
- Elke A. Rundensteiner, Daniel Gajski, Lubomir Bic:
The Component Sythesis Algorithm: Technology Mapping for Register Transfer Descriptions. 208-211 - Rajiv Jain:
MOSP: Module Selection for Pipelined Designs with Multi-Cycle Operations. 212-215 - Rajesh K. Gupta, Giovanni De Micheli:
Partitioning of Functional Models of Synchronous Digital Systems. 216-219
Session 5C: Automatic Test Pattern Generation
- Udo Mahlstedt, Torsten Grüning, Cengiz Özcan, Wilfried Daehn:
Contest: A Fast ATPG Tool for Very Large Combinatorial Circuits. 222-225 - Kwang-Ting Cheng, Jing-Yang Jou:
A Single-State-Transition Fault Model for Sequential Machines. 226-229 - Chun-Hung Chen, Jacob A. Abraham:
Mixed-Level Sequential Test Generation Using a Nine-Valued Relaxation Algorithm. 230-233
Session 6A: Layout Desgin and Verification
- Krishna P. Belkhale, Prithviraj Banerjee:
A Parallel Algorithm for Hierarchical Circuit Extraction. 236-239 - Hirotoshi Sawada:
A Hierarchical Circuit Extractor Based on New Cell Overlap Analysis. 240-243 - William J. Grundmann, Yao-Tsung Yen:
XREF/COUPLING: Capacitive Coupling Error Checker. 244-247 - Jean-Claude Dufourd, Jean-François Naviner, Francis Jutand:
Preform: A Process Independent Symbolic Layout System. 248-251
Session 6B: Scheduling and Allocation
- D. L. Springer, Donald E. Thomas:
Exploiting the Special Structure of Conflict and Compatibility Graphs in High-Level Synthesis. 254-257 - Catherine H. Gebotys, Mohamed I. Elmasry:
A Global Optimization Approach for Architectural Synthesis. 258-261 - John A. Nestor, Ganesh Krishnamoorthy:
SALSA: A New Approach to Scheduling with Timing Constraints. 262-265
Session 6C: Topics in Testing
- Susana Stoica:
A Hierarchical Approach for Testing Large Circuits. 268-271 - Manfred Geilert, Jürgen Alt, Michael Zimmermann:
On the Efficiency of the Transition Fault Model for Delay Faults. 272-275 - Scott H. Robinson, John Paul Shen:
Evaluation and Synthesis of Self-Monitoring State Machines. 276-279 - Weiwei Mao, Ravi K. Gulati, Deepak K. Goel, Michael D. Ciletti:
QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults. 280-283
Session 7A: Analog Design and Test
- Gani Jusuf, Paul R. Gray, Alberto L. Sangiovanni-Vincentelli:
CADICS - Cyclic Analog-to-Digital Converter Synthesis. 286-289 - Dale E. Hocevar, Rajeev Arora, Uttiya Dasgupta, Sattam Dasgupta, Nagaraj Subramanyam, Sham Kashyap:
A Usable Circuit Optimizer for Designers. 290-293 - Linda Milor, Alberto L. Sangiovanni-Vincentelli:
Optimal Test Set Design for Analog Circuits. 294-297
Session 7B: Datapath Synthesis
- David Knapp:
Feedback-Driven Datapath Optimization in Fasolt. 300-303 - Christian Ewering:
Automatic High Level Syntesis of Partitioned Busses. 304-307 - Fur-Shing Tsai, Yu-Chin Hsu:
Data Path Construction and Refinement. 308-311
Session 7C: Partial Scan and Test Minimization
- Kee Sup Kim, Charles R. Kime:
Partial Scan by Use of Empirical Testability. 314-317 - Tsu-Wei Ku, Wei-Kong Chia:
Test Vector Minimization During Logic Synthesis. 318-321 - Dong-Ho Lee, Sudhakar M. Reddy:
On Determining Scan Flip-Flops in Partial-Scan Designs. 322-325
Session 8A: Placement
- Michael A. B. Jackson, Arvind Srinivasan, Ernest S. Kuh:
A Fast Algorithm for Performance-Driven Placement. 328-331 - Stefan Mayrhofer, Ulrich Lauther:
Congestion-Driven Placement Using a New Multi-Partitioning Heuristic. 332-335 - William Swartz, Carl Sechen:
New Algorithms for the Placement and Routing of Macro Cells. 336-339 - Cheryl Harkness, Daniel P. Lopresti:
VLSI Placement Using Uncertain Costs. 340-343
Session 8B: Design Management in CAD Frameworks
- Wayne Allen, Douglas Rosenthal, Kenneth W. Fiduk:
Distributed Methodology Management for Design-in-the-Large. 346-349 - Felix Bretschneider, Christa Kopf, Helmut Lagger, Arding Hsu, Elizabeth Wei:
Knowledge Based Design Flow Management. 350-353 - Toshiaki Miyazaki, Tamio Hoshino, Makoto Endo:
A CAD Process Scheduling Technique. 354-357 - Tzi-cker Chiueh, Randy H. Katz:
A History Model for Managing the VLSI Design Process. 358-361
Session 8C: Built-In Self Test and Diagnostics
- Janusz Rajski, Jerzy Tyszer, Babak Salimi:
On the Diagnostic Resolution of Signature Analysis. 364-367 - André Ivanov, Yervant Zorian:
Computing the Error Escape Probability in Count-Based Compaction Schemes. 368-371 - Paul G. Ryan, W. Kent Fuchs:
Partial Detectability Profiles. 372-375
Session 9A: Technology Driven Routing
- Ikuo Harada, Hitoshi Kitazawa, Takao Kaneko:
A Routing System for Mixed A/D Standard Cell LSIs. 378-381 - Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic:
A Detailed Router for Field-Programmable Gate Arrays. 382-385 - Akihiko Hanafusa, Yasuhiro Yamashita, Mitsuru Yasuda:
Three-Dimensional Routing for Multilayer Ceramic Printed Circuit Boards. 386-389
Session 9B: Reliability Simulation
- Hansruedi Heeb, Albert E. Ruehli, J. Janak, Shahrokh Daijavad:
Simulating Electromagnetic Radiation of Printed Circuit Boards. 392-395 - Ulrich Jagau:
SIMCURRENT: An Efficient Program for the Estimation of the Current Flow of Complex CMOS Circuits. 396-399 - Yusuf Leblebici, Sung-Mo Kang:
An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis. 400-403
Session 9C: Sequential Optimization
- Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda:
Multi-Level Logic Minimization Across Latch Boundaries. 406-409 - Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Performance Optimization of Pipelined Circuits. 410-413 - Bill Lin, Hervé J. Touati, A. Richard Newton:
Don't Care Minimization of Multi-Level Sequential Logic Networks. 414-417
Session 10A: Routing Algorithms and Complexity 2
- Masato Edahiro:
A Clock Net Reassignment Algorithm Usign Voronoi Diagram. 420-423 - Jan-Ming Ho, Majid Sarrafzadeh, Atsushi Suzuki:
An Exact Algorithm for Single-Layer Wire-Length Minimization. 424-427 - Andrew B. Kahng, Gabriel Robins:
A New Class of Steiner Trees Heuristics with Good Performance: The Iterated 1-Steiner-Approach. 428-431 - Ting-Hai Chao, Yu-Chin Hsu:
Rectilinear Steiner Tree Construction by Local and Global Refinement. 432-435
Session 10B: Parallel Matrix Techniques
- John A. Trotter, Prathima Agrawal:
Circuit Simulation Algorithms on a Distributed Memory Multiprocessor System. 438-441 - Luís Miguel Silveira, Andrew Lumsdaine, Jacob White:
Parallel Simulation Algorithms for Grid-Based Analog Signal Processors. 442-445 - Kartikeya Mayaram, Ping Yang, Jue-Hsien Chern, Richard Burch, Lawrence A. Arledge Jr., Paul F. Cox:
A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device Simulations. 446-449 - John A. Trotter, Prathima Agrawal:
Fast Overlapped Scattered Array Storage Schemes for Sparse Matrices. 450-453
Session 10C: Synthesis for Test and Diagnosis
- Michael J. Bryan, Srinivas Devadas, Kurt Keutzer:
Testability-Preserving Circuit Transformations. 456-459 - Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng:
Timing Optimization with Testability Considerations. 460-463 - Heh-Tyan Liaw, Jia-Horng Tsaih, Chen-Shang Lin:
Efficient Automatic Diagnosis of Digital Circuits. 464-467 - Masahiro Tomita, Hong-Hai Jiang, Tamotsu Yamamoto, Yoshihiro Hayashi:
An Algorithm for Locating Logic Design Errors. 468-471
Session 11A: Exploratory Initiatives in CAD Frameworks
- Jukka Lahti, Jorma Kivelä:
Logic Compilation from Graphical Dependency Notation. 474-477 - Nishit P. Parikh, Chi-Yuan Lo, Anoop Singhal, Kwok W. Wu:
HS: A Hierarchical Search Package for CAD Data. 478-481 - Peter van den Hamer, Menno Treffers:
A Data Flow Based Architecture for CAD Frameworks. 482-485
Session 11B: Switch and Logic Simulation
- Ibrahim N. Hajj:
An Algebra for Switch-Level Simulation. 488-491 - Kuen-Jong Lee, Rajiv Gupta, Melvin A. Breuer:
A New Method for Assigning Signal Flow Directions to MOS Transistors. 492-495 - Vishwani D. Agrawal, Srimat T. Chakradhar:
Logic Simulation and Parallel Processing. 496-499
Session 11C: Combinatorial Optimization
- Maurizio Damiani, Giovanni De Micheli:
Observability Don't Care Sets and Boolean Relations. 502-505 - F. Crowet, Marc Davio, C. Dierieck, J. Durieu, G. Louis, Chantal Ykman-Couvreur:
PHIFACT, a Boolean Preprocessor for Multi-Level Logic Synthesis. 506-509 - Jagadeesh Vasudevamurthy, Janusz Rajski:
A Method for Concurrent Decomposition and Factorization of Boolean Expressions. 510-513
Session 12A: Partitioning and Module Generation
- Yen-Chuen A. Wei, Chung-Kuan Cheng:
A Two-Level Two-Way Partitioning Algorithm. 516-519 - Jörn Garbers, Hans Jürgen Prömel, Angelika Steger:
Finding Clusters in VLSI Circuits. 520-523 - T. W. Her, D. F. Wong, T. H. Freeman:
Optimal Orientations of Transistor Chains. 524-527 - John Conway, Gerard F. M. Beenker:
A New Template Based Approach to Module Generation. 528-531
Session 12B: Linear Circuit Simulation
- Xiaoli Huang, Vivek Raghavan, Ronald A. Rohrer:
AWEsim: A Program for the Efficient Analysis of Linear(ized) Circuits. 534-537 - John Y. Lee, Xiaoli Huang, Ronald A. Rohrer:
Efficient Pole Zero Sensitivity Calculation in AWE. 538-541 - Tak K. Tang, Michel S. Nakhla:
Analysis of High-Speed VLSI Interconnects Using the Asymptotic Waveform Evaluation Technique. 542-545 - Douglas R. Holberg, Santanu Dutta, Lawrence T. Pillage:
DC Parameterized Piecewise-Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation. 546-549
Session 12C: Synthesis Systems
- Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun:
check Tc and min Tc: Timing Verification and Optimal Clocking of Synchronous Digtal Circuits. 552-555 - Kaname Kuroki, Nobuyoshi Nomizu, Shigenobu Suzuki, Kazutoshi Takahashi:
A Framework Environment for Logic Design Support System. 556-559 - Luciano Lavagno, Sharad Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs. 560-563 - Akira Nagoya, Yukihiro Nakamura, Kiyoshi Oguri, Ryo Nomura:
Multi-Level Optimization for Large Scale ASICS. 564-567
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