ICCD 2000:
Austin, Texas, USA
Proceedings of the IEEE International Conference On Computer Design:
VLSI In Computers & Processors (ICCD '00), September 17-20, 2000, Austin, Texas, USA. IEEE Computer Society, 2000
Keynote Address
- Dirk Friebel:
On the Road to a Mobile Information Society.
3-
Session 1.1:
New Architectures
Session 1.2:
Fault-Simulation and ATPG at Different Design Levels
Session 1.3:
Advanced Design Techniques
- Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang:
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology.
59-64
- Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits.
65-72
- Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson:
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems.
73-
Session 2.1:
Improving CPU Performance
Session 2.2:
Parasitic Modeling, Analysis, and Optimization
Session 2.3:
Low Power and Arithmetic
Session 3.1:
Servers and Parallelism
Session 3.2:
Circuit Optimization and Analysis
Session 3.3:
Logic Circuit Families
Keynote Address
Session 4.1:
Intelligent Memory
Session 4.2:
Processor Microarchitecture
Session 4.3:
Digital Logic Techniques
Session 5.1:
Embedded Processors:
Architecture and System-Design Issues
Session 5.2:
Floorplanning and Partitioning
Session 5.3:
Basic Algorithms in Verification and Test
Session 6.1:
Special Session:
Advancements in DSP Architecture
Session 6.2:
Advanced Architectural Design and Synthesis
- Srihari Cadambi, Seth Copen Goldstein:
Efficient Place and Route for Pipeline Reconfigurable Architectures.
423-429
- Makiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi:
PEAS-III: An ASIP Design Environment.
430-436
- Satish Pillai, Margarida F. Jacome:
Symbolic Binding for Clustered VLIW ASIPs.
437-444
- Dinesh Ramanathan, Rajesh K. Gupta, Raymond Roth:
Interfacing Hardware and Software Using C++ Class Libraries.
445-
Session 6.3:
Application and Case Studies in Test and Verification
- Hoon Choi, Myung-Kyoon Yim, Jae Young Lee, Byeong-Whee Yun, Yun-Tae Lee:
Formal Verification of an Industrial System-on-a-Chip.
453-458
- Viresh Paruthi, Andreas Kuehlmann:
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation.
459-464
- Dirk W. Hoffmann, Thomas Kropf:
Efficient Design Error Correction of Digital Circuits.
465-472
- Michael Cogswell, Don Pearl, James Sage, Alan Troidl:
An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design.
473-
Invited Paper
Session 7.1:
Logic Optimization
Session 7.2:
High Level Specification and Synthesis
- Wander O. Cesário, Ahmed Amine Jerraya, Zoltan Sugar, Imed Moussa:
Rethinking Behavioral Synthesis for a Better Integration within Existing Design Flows.
513-518
- Bong-Il Park, Hoon Choi, In-Cheol Park, Chong-Min Kyung:
Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies.
519-524
- Fabiano Hessel, Philippe Coste, Gabriela Nicolescu, P. LeMarrec, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya:
Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification.
525-
Poster Sessions
- Wael M. Badawy, Magdy A. Bayoumi:
Low Power Video Object Motion-Tracking Architecture for Very Low Bit Rate Online Video Applications.
533-536
- Alfredo Benso, Stefano Martinetto, Paolo Prinetto, Riccardo Mariani:
An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications.
537-538
- Alfredo Benso, Stefano Di Carlo, Silvia Chiusano, Paolo Prinetto, Fabio Ricciato, Monica Lobetti Bodoni, Maurizio Spadari:
On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs.
539-540
- Haizhou Chen, Bing Lu, Ding-Zhu Du:
Static Timing Analysis with False Paths.
541-544
- Joachim Gerlach, Wolfgang Rosenstiel:
A Methodology and Tool for Automated Transformational High-Level Design Space Exploration.
545-548
- J. P. Grossman:
Cheap Out-of-Order Execution Using Delayed Issue.
549-551
- Steve Haynal, Forrest Brewer:
Representing and Scheduling Looping Behavior Symbolically.
552-555
- Toru Hiyama, Yuko Ito, Satoru Isomura, Kazunobu Nojiri, Eijiro Maeda:
Advanced Wiring RC Timing Design Techniques for Logic LSIs in Gigahertz Era and Beyond.
556-558
- Yoochang Jung, Stefan G. Berg, Donglok Kim, Yongmin Kim:
A Register File with Transposed Access Mode.
559-560
- Kamal S. Khouri, Niraj K. Jha:
Leakage Power Analysis and Reduction during Behavioral Synthesis.
561-564
- Austin Kim, J. Morris Chang:
An Advanced Instruction Folding Mechanism for a Stackless Java Processor.
565-566
- Hemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha Chandrakasan:
OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet.
567-570
- Haris Lekatsas, Jörg Henkel, Wayne Wolf:
A Decompression Architecture for Low Power Embedded Systems.
571-574
- Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh:
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures.
575-576
- Afzal Malik, Bill Moyer, Dan Cermak:
The M·CORETM M340 Unified Cache Architecture.
577-580
- Song-Ra Pan, Yao-Wen Chang:
Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation.
581-584
- Marius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra:
Hierarchical Simulation of a Multiprocessor Architecture.
585-588
- Hagen Ploog, Dirk Timmermann:
On Multiple Precision Based Montgomery Multiplication without Precomputation of N0´ = -N0-1 mod W.
589-590
- Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana:
A Technique for Identifying RTL and Gate-Level Correspondences.
591-
- John T. Welch, Joan Carletta:
A Direct Mapping FPGA Architecture for Industrial Process Control Applications.
595-598
- Brian D. Winters, Alan J. Hu:
Source-Level Transformations for Improved Formal Verification.
599-
Last update Thu May 23 16:59:47 2013
CET by the DBLP Team — 
Data released under the ODC-BY 1.0 license — See also our legal information page
