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ORCID22nd ISMVL 1992: Sendai, Japan
- 22nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 1992, Sendai, Japan, May 27-29, 1992, Proceedings. IEEE Computer Society 1992, ISBN 0-8186-2680-1
Session 1: Invited Address
- Shinya Hasuo:
High-Speed Digital Circuits for a Josephson Computer. 2-8
Session 2A: Device-Based Circuit
- Mititada Morisue, Fu-Qiang Li:
A Superconducting Ternary Systolic Array Processor. 10-17 - Lutz J. Micheel:
Heterojunction Bipolar Technology for Emitter-Coupled Multiple-Valued Logic in Gigahertz Adders and Multipliers. 18-26 - Sen Jung Wei, Hung Chang Lin:
Unique Folding and Hysteresis Characteristics of RTD for Multi-Valued Logic and Counting Applications. 27-33
Session 2B: Test
- Naotake Kamiura, Yutaka Hata, Fujio Miyawaki, Kazuharu Yamato:
Easily Testable Multiple-Valued Cellular Arrays. 36-42 - Geetani Edirisooriya, John P. Robinson:
Aliasing in Multiple-Valued Test Data Compaction. 43-50 - Hassan M. Razavi, Paul W. Wong:
A New Balanced Gate for Structural Testing. 51-55
Session 3A: Logic Minimization
- Gerhard W. Dueck:
Direct Cover MVL Minimization with Cost-Tables. 58-65 - Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler:
Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. 66-74 - Chyan Yang, Onur Oral:
Experiences of Parallel Processing with Direct Cover Algorithms for Multiple-Valued Logic Minimization. 75-82
Session 3B: Neural Network
- Chia-Lun J. Hu:
Design of a 4-Valued Digital Multiplier Using an Artificial Heterogeneous Two-Layered Neural Network. 84-87 - Tatsuki Watanabe, Masayuki Matsumoto:
Layered MVL Neural Networks Capable of Recognizing Translated Characters. 88-95 - Joo-Hwee Lim, Ho-Chung Lui, Hoon heng Teh:
A Deductive Neural-Logic System. 96-102
Session 4A: Circuit Design
- Konrad Lei, Zvonko G. Vranesic:
Towards the Realization of 4-Valued CMOS Circuits. 104-110 - Mostafa I. H. Abd-El-Barr, H. Choy:
Incremental Gate: A Method to Compute Minimal Cost CCD Realizations of MVL Functions. 111-118 - Xunwei Wu:
The Theory of Clipping Voltage-Switches and Design of Quaternary nMOS Circuits. 119-125
Session 4B: Algebra 1
- Takahiro Haga:
An Application of the p-Valued Input, q-Kind-Valued Output Logic to the Synthesis of the p-Valued Logical Networks. 128-137 - Kiyomichi Araki, Masayuki Takada, Masakatu Morii:
On the Efficient Decoding of Reed-Solomon Codes Based on GMD Criterion. 138-145 - Patrick Doherty, Witold Lukaszewicz:
Defaults as First-Class Citizens. 146-154
Session 5: Invited Address
- Daniel Etiemble:
On the Performance of Multivalued Integrated Circuits: Past, Present and Future. 156-164
Session 6A: Reliable Systems
- David Wessels, Jon C. Muzio:
Concurrent Checking and Unidirectional Errors in Multiple-Valued Circuits. 166-173 - Masayoshi Sakai, Masakazu Kato, Koichi Futsuhara, Masao Mukaidono:
Application of Fail-Safe Multiple-Valued Logic to Control of Power Press. 174-180 - Hui Min Wang, Chung-Len Lee, Jwu E. Chen:
Fault Analysis on Two-Level (K+1)-Valued Logic Circuits. 181-188
Session 6B: Algebra 2
- M. C. Canals Frau, Aldo V. Figallo:
(n+1)-Valued Modal Implicative Semilattices. 190-196 - Jizhong Shen:
Fuzzifying Topological Groups Based on Completely Distributive Residuated Lattice-Valued Logic (I). 198-205
Session 7A: Current Mode Circuits
- Edward K. F. Lee, P. Glenn Gulak:
Dynamic Current-Mode Multi-Valued MOS Memory with Error Correction. 208-215 - Kazutaka Taniguchi, Mamoru Sasaki, Yutaka Ogata, Fumio Ueno, Takahiro Inoue:
Bi-CMOS Current Mode Multiple Valued Logic Circuits with 1.5V Supply Voltage. 216-220 - Mostafa I. H. Abd-El-Barr, M. I. Mahroos:
On the Synthesis of MVL Functions for Current-Mode CMOS Circuits Implementation. 221-228 - K. Wayne Current:
A Current-Mode CMOS Algorithmic Analog-to-Quaternary Converter Circuit. 229-234
Session 7B: Algebra 3
- Kyoichi Nakashima, Noboru Takagi:
On Multiple-Valued Logic Functions Monotonic with Respect to Ambiguity. 236-242 - Noboru Takagi, Kyoichi Nakashima, Masao Mukaidono:
Fundamental Properties of Extended Kleene-Stone Logic Functions. 243-249 - Ratko Tosic, Ivan Stojmenovic, Dan A. Simovici, Corina Reischer:
On Set-Valued Functions and Boolean Collections. 250-254 - Reinhard Pöschel, M. Reichel:
Rectangular Algebras. 255-260
Session 8: Invited Address
- Marek A. Perkowski:
A Universal Logic Machine. 262-271
Session 9A: VLSI 1
- Takahiro Hanyu, Kouichi Takeda, Tatsuo Higuchi:
Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems. 274-281 - Shuichi Maeda, Takafumi Aoki, Tatsuo Higuchi:
Set-Valued Logic Networks Based on Optical Wavelength Multiplexing. 282-290 - Jonathan W. Mills:
Area-Efficient Implication Circuits for Very Dense Lukasiewicz Logic Arrays. 291-298
Session 9B: Completeness
- Masahiro Miyakawa, Akihiro Nozaki, Grant Pogosyan, Ivo G. Rosenberg:
Semigrid Sets of Central Relations Over a Finite Domain. 300-307 - V. Lashkia:
Amplification of the Functional Closure Operation. 308-311
Session 10: Invited Address
- Ágnes Szendrei:
A Completeness Criterion for Semi-Affine Algebras. 314-319
Session 11A: VLSI 2
- Katsuhiko Shimabukuro, Michitaka Kameyama, Tatsuo Higuchi:
Design of a Multiple-Valued VLSI Processor for Digital Control. 322-329 - Makoto Honda, Michitaka Kameyama, Tatsuo Higuchi:
Residue Arithmetic Based Multiple-Valued VLSI Image Processor. 330-336 - Shoji Kawahito, Y. Mitsui, Makoto Ishida, Tetsuro Nakamura:
Parallel Hardware Algorithms with Redundant Number Representations for Multiple-Valued Arithmetic VLSI. 337-345
Session 11B: Spectral Techniques
- Philipp W. Besslich, Eliezer A. Trachtenberg:
Binary Input/Ternary Output Switching Circuits Designed Via the Sign Transformation. 348-354 - Randal Tomczuk, D. Michael Miller:
Autocorrelation Techniques for Multi-Bit Decoder PLAs. 355-364 - Radomir S. Stankovic:
Some Remarks on Fourier Transform and Differential Operators for Digital Functions. 365-370
Session 12: Special Session
- Susan W. Butler, Jon T. Butler:
Profiles of Topics and Authors of the International Symposium on Multiple-Valued Logic for 1971-1991. 372-379
Session 13A: Logic Design
- Saneaki Tamaki, Michitaka Kameyama, Tatsuo Higuchi:
Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits. 382-388 - Yutaka Hata, Fujio Miyawaki, Kazuharu Yamato:
Optimal Output Assignment and the Maximum Number of Implicants Needed to Cover the Multiple-Valued Logic Functions. 389-395 - Mou Hu, Shensheng Xu, Kenneth C. Smith:
On the Use of Multiple-Valued Switch-Level Algebra to Analyze Binary MOS Bridge Circuits and Dynamic Circuits. 396-400 - Benchu Fei, Nan Zhuang:
Fast Logic Synthesis Based Upon Ternary Universal Logic Module f. 401-407
Session 13B: Fuzzy Logic 1
- Fumio Ueno, Takahiro Inoue, Badur-ul-Haque Baloch, Takayoshi Yamamoto:
An Automatic Adjustment Method of Backpropagation Learning Parameters, Using Fuzzy Inference. 410-414 - Yoshinori Yamamoto:
A Meaningful Infinite-Valued Switching Function - Fuzzy Threshold Function and Its Application to Process Control. 415-422 - Yuji Shirai, Fumio Ueno, Takahiro Inoue, Motohiro Inoue, Kouji Tasaki:
Inverted Pendulum Controlled Circuit Using Fuzzy State Memory with Voltage Mode Fuzzy State Memory. 423-427 - Hiroshi Ito, Takashi Matsubara, Takakazu Kurokawa, Yoshiaki Koga:
A Proposal of Fault-Checking Fuzzy Control. 428-434
Session 14A: EXOR Logic
- Berthold Harking, Claudio Moraga:
Efficient Derivation of Reed-Muller Expansions in Multiple-Valued Logic Systems. 436-441 - Marek A. Perkowski:
The Generalized Orthonormal Expansion of Functions with Multiple-Valued Inputs and Some of Its Applications. 442-450 - Tsutomu Sasao:
Optimization of Multiple-Valued AND-EXOR Expressions Using Multiple-Place Decision Diagrams. 451-458
Session 14B: Fuzzy Logic 2
- Akira Nakamura:
On a Logic Based on Fuzzy Modalities. 460-466 - Zuliang Shen, Liya Ding, Ho-Chung Lui, Pei-Zhuang Wang, Masao Mukaidono:
Revision Principle for Approximate Reasoning-Based on Semantic Revising Method. 467-473 - Heinz J. Skala:
On Yager's Aggregation Operators. 474-477
Session 15: Invited Address
- Lotfi A. Zadeh:
Fuzzy Logic and the Calculus of Fuzzy If-Then Rules. 480
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