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ORCID23rd ISMVL 1993: Sacramento, California, USA
- 23rd IEEE International Symposium on Multiple-Valued Logic, ISMVL 1993, Sacramento, California, USA, May 24-27, 1993, Proceedings. IEEE Computer Society 1993, ISBN 0-8186-3350-6
Session 1: Invited Address
- D. Michael Miller:
Multiple-Valued Logic Design Tools. 2-11
Session 2a: Logic Minimization
- Qinhua Hong, Benchu Fei, Haomin Wu, Marek A. Perkowski, Nan Zhuang:
Fast Synthesis for Ternary Reed-Muller Expansion. 14-16 - Cem Yildirim, Jon T. Butler, Chyan Yang:
Multiple-Valued PLA Minimization by Concurrent Multiple and Mixed Simulated Annealing. 17-23 - Antonio Lloris-Ruíz, Juan Francisco Gómez-Lopera, Ramón Román-Roldán:
Entropic Minimization of Multiple-Valued Functions. 24-28 - Yutaka Hata, Takahiro Hozumi, Kazuharu Yamato:
Gate Model Networks for Minimization of Multiple-Valued Logic Functions. 29-34
Session 2b: Logic
- Noboru Takagi, Kyoichi Nakashima, Masao Mukaidono:
A Canonical Disjunctive Form of Extended Kleene-Stone Logic Functions. 36-41 - Zuoquan Lin:
Three-Valued Nonmonotonic Logic. 42-47 - James J. Lu, Neil V. Murray, Erik Rosenthal:
Signed Formulas and Annotated Logics. 48-53 - E. R. Harley, Zbigniew Stachniak:
Minimal Resolution Proof Systems for Finitely-Valued Lukasiewicz Logics. 54-59
Session 3a: Fuzzy Logic
- Helmut Thiele:
On the Definition of Modal Operators in Fuzzy Logic. 62-67 - Zhenfeng Wang, Dongming Jin, Zhijian Li:
Single-Chip Realization of a Fuzzy Logic Controller with Neural Network Structure (NNFLC). 68-73 - Laurent Lemaitre, Marek J. Patyra, Daniel Mlynek:
Synthesis and Design Automation of Analog Fuzzy Logic VLSI Circuits. 74-79
Session 3b: Testing
- Haomin Wu, Nan Zhuang, Marek A. Perkowski:
Novel CMOS Scan Design for VLSI Testability. 82-86 - Yasunori Nagata, Chushin Afuso:
A Method of Test Pattern Generation for Multiple-Valued PLA's. 87-91 - Naotake Kamiura, Yutaka Hata, Kazuharu Yamato:
A Repairable and Diagnosable Cellular Array on Multiple-Valued Logic. 92-97
Session 4a: Algebra I
- Dan A. Simovici, Corina Reischer:
On Functional Entropy. 100-104 - Akihiro Nozaki, Grant Pogosyan, Masahiro Miyakawa, Ivo G. Rosenberg:
Semirigid Sets of Quasilinear Clones. 105-110 - Renren Liu:
Some Results on the Decision and Construction for Sheffer Functions in Partial K-Valued Logic. 111-116
Session 4b: Function Decomposition and Minimization
- Sami B. Abugharbieh, Samuel C. Lee:
A Fast Algorithm for the Disjunctive Decomposition of m-Valued Functions Part I: The Decomposition Algorithm. 118-125 - Sami B. Abugharbieh, Samuel C. Lee:
A Fast Algorithm for the Disjunctive Decomposition of m-Valued Functions Part II: Time Complexity Analysis. 126-131 - Ning Song, Marek A. Perkowski:
EXORCISM-MV-2: Minimization of Exclusive Sum of Products Expressions for Multiple-Valued Input Incompletely Specified Functions. 132-137
Session 5: Invited Address
- Takafumi Aoki:
Dreams for New-Device-Based Superchips: From Transistors to Enzymes. 140-149
Session 6a: Circuits
- Shinji Karasawa, Kazuhiko Yamanouchi:
Design and Examination of a Multiple-Valued Flip-Flop Circuit with Stair Shaped I-V Curved Device as a Coupling Element. 152-157 - Ming-Huei Shieh, Hung Chang Lin:
Series Resonant Tunneling Diodes as a Two-Dimensional Memory Cell. 158-163 - Lutz J. Micheel, Albert H. Taddiken, Alan C. Seabaugh:
Multiple-Valued Logic Computation Circuits Using Micro- and Nanoelectronic Devices. 164-169 - Satoshi Aragaki, Takahiro Hanyu, Tatsuo Higuchi:
A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions. 170-175 - K. Wayne Current:
Multiple Valued Logic: Current-Mode CMOS Circuits. 176-181
Session 6b: Learning and Reasoning
- Kiyotaka Miyai, Yutaka Hata, Kazuharu Yamato:
A Representation of Approximate Reasoning with Analogy. 184-189 - Shyi-Ming Chen:
An Inexact Reasoning Technique Using Linguistic Rule Matrix Transformations. 190-195 - Zheng Tang, Okihiko Ishizuka, Qixin Cao, Hiroki Matsumoto:
Algebraic Properties of a Learning Multiple-Valued Logic Network. 196-201 - Qixin Cao, Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto:
Algorithm and Implementation of a Learning Multiple-Valued Logic Network. 202-207 - Matthias Baaz, Christian G. Fermüller, Richard Zach
:
Systematic Construction of Natural Deduction Systems for Many-Valued Logics. 208-213
Session 7a: Logic Design
- Daniel Etiemble, Keivan Navi:
A Basis for the Comparison of Binary and m-Valued Current Mode Circuits: the Multioperand Addition with Redundant Number Systems. 216-221 - Yutaka Hata, Kazuharu Yamato:
Multiple-Valued Logic Functions Represented by TSUM, TPRODUCT, NOT and Variables. 222-227 - Noriaki Muranaka, Shigeru Imanishi, D. Michael Miller:
Decimal Addition and Subtraction Units Using the p-Valued Decimal Signed-Digit Number Representation. 228-233
Session 7b: Algebra II
- Benchu Fei, Qinhua Hong, Nan Zhuang:
Calculation of Ternary Mixed Polarity Function Vector. 236-238 - Xiexiong Chen, Claudio Moraga:
An Algebra for Current-Mode CMOS Multivalued Circuits. 239-244 - Zeljko Zilic, Zvonko G. Vranesic:
Current-Mode CMOS Galois Field Circuits. 245-250 - Dan A. Simovici, Ivan Stojmenovic, Ratko Tosic:
Functional Completeness and Weak Completeness in Set Logic. 251-256
Session 8: Invited Address
- Jonathan W. Mills:
Lukasiewicz' Insect: The Role of Continuous-Valued Logic in a Mobile Robot's Sensors, Control, and Locomotion. 258-263
Session 9a: Special Applications
- Babak A. Taheri:
CMOS Implementation and Fabrication of the Pseudo Analog Neuron. 266-270 - Takafumi Aoki, Tatsuo Higuchi:
Impact of Interconnection-Free Biomolecular Computing. 271-276 - Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi:
Design of Set-Valued Logic Networks for Wave-Parallel Computing. 277-282 - Masami Nakajima, Michitaka Kameyama:
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations. 283-288
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