ITC 1996: Washington, DC, USA

Session 1: Plenary

Session 2.0: Automatic Test Generation

Session 3.0: BIST: Architectures and Generation

Session 4.0: New Test Considerations for Mixed-Signal Devices

Session 5.0: Topics in Test Hardware

Session 6.0: Practical and Higher-Level Fault Simulation

Session 7.0: BIST Pattern Generation

Session 8.0: Testing of Asynchronous Circuits

Session 9.0: Industry Impact: Screeninig, Test, and Measurement Breakthroughs

Session 10.0: Fault Simulation and Diagnosis of Delay Faults

Session 11.0: Memory Test: Design for Testability

Session 12.0: Board Test Challenges and Solutions

Session 13.0: Delay-Fault Testing 1

Session 14.0: Microprocessor Test

Session 15.0: An Evolving Mixed-Signal Boundary-Scan Standard

Session 16.0: Delay-Fault Testing 2

Session 17.0: Software for New Test Strategies

Session 18.0: Innovations in Current Testing

Session 19.0: Mixed-Signal DFT and Fault Simulation

Session 20.0: DFT: Inching Forward with Partial-Scan Design

Session 21.0: Test Languages and Tools

Session 22.0: Application of SPC to IC Design, Manufacturing and Test

Session 23.0: New Techniques for Realistic Faults

Session 24.0: Design-for-Testability Inspirations

Session 25.0: High Frequency and Timing in ATE

Session 26.0: Topics in Test Engineering

Session 27.0: System Test: Practical Aspects, Partitioning and Simulation

Session 28.0: Test Synthesis Solutions

Session 29.0: Advanced Fault Modelling Techniques

Session 30.0: Test Economic Issues

Session 31.0: MCM Test: Methods and Applications

Session D1.0: Design Validation: Methodologies and Case Studies

Session D2.0: Hybrid Validation and Test Techniques

Session D3.0: Design Validation: From System Specification to Process Effects

Session L1: Unpowered Opens Testing

Session L2: Practical Aspects of IC Diagnosis & Failure Analysis: A Walk Through the Process

Panel 1: Why Do We Talk about DFT When the Problem is Bad Design and Bad CAD Tools?

Panel 2: Asynchronous Design: Nightmare or Opportunity?

Panel 5: DFT for Embedded Cores

Panel 6: What Are the Next Generation Test Methodologies for Board and System Test?

Panel 7: Will I-DDQ Testing Leak Away in Deep Sub-Micron Technology?