Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDITC 1998: Washington, DC, USA
- Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998. IEEE Computer Society 1998, ISBN 0-7803-5093-6
Session 1: Plenary
Session 2: Escaping The High Cost of Test Escapes
- Wayne M. Needham, Cheryl Prunty, Yeoh Eng Hong:
High volume microprocessor test escapes, an analysis of defects our tests are missing. 25-34 - Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Defect-oriented test quality assessment using fault sampling and simulation. 35-42 - Phil Nigh, David P. Vallett, Atul Patel, Jason Wright:
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment. 43-52
Session 3: Memory Test Algorithms and Pattern Generation
- Jan Otterstedt, Dirk Niggemeyer, T. W. Williams:
Detection of CMOS address decoder open faults with March and pseudo random memory tests. 53-62 - Said Hamdioui, Ad J. van de Goor:
Consequences of port restrictions on testing two-port memories. 63-72 - Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty:
A new framework for generating optimal March tests for memory arrays. 73-82
Session 4: DFT in Practice
- Pamela S. Gillis, Francis Woytowich, Kevin McCauley, Ulrich Baur:
Delay test of chip I/Os using LSSD boundary scan. 83-90 - Karim Arabi, Hassan Ihs, Christian Dufaza, Bozena Kaminska:
Digital oscillation-test method for delay and stuck-at fault testing of digital circuits. 91-100 - E. Kofi Vida-Torku, George Joos:
Designing for scan test of high performance embedded memories. 101-108
Session 5: Thermal Issues in Manufacturing Test
- Andreas C. Pfahnl, John H. Lienhard V
, Alexander H. Slocum:
Maximizing handler thermal throughput with a rib-roughened test tray. 109-113 - Andreas C. Pfahnl, John H. Lienhard V, Alexander H. Slocum:
Temperature control of a handler test interface. 114-118 - Mark Malinoski, James Maveety, Steve Knostman, Tom Jones:
A test site thermal control system for at-speed manufacturing testing. 119-128
Session 6: Embedded Cores
- Yervant Zorian, Erik Jan Marinissen, Sujit Dey:
Testing embedded-core based system chips. 130-143
Session 7: BIST Synthesis
- Zhe Zhao, Bahram Pouya, Nur A. Touba:
BETSY: synthesizing circuits for a specified BIST environment. 144-153 - Han Bin Kim, Takeshi Takahashi, Dong Sam Ha:
Test session oriented built-in self-testable data path synthesis. 154-163 - Srinivas Devadas, Kurt Keutzer:
An algorithmic approach to optimizing fault coverage for BIST logic synthesis. 164-173
Session 8: Experimental Results in Current Testing
- Anne E. Gattiker, Wojciech Maly:
Toward understanding "Iddq-only" fails. 174-183 - Jonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey:
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip. 184-193 - Alan W. Righter, Charles F. Hawkins, Jerry M. Soden, Peter C. Maxwell:
CMOS IC reliability indicators and burn-in economics. 194-203 - Manoj Sachdev, Peter Janssen, Victor Zieren:
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs. 204
Session 9: MCM Test - Theory and Applications
- Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian:
A distributed BIST technique for diagnosis of MCM interconnections. 214-221 - Alex S. Biewenga, Math Muris, Rodger Schuttert, Urs Fawer:
Testing a multichip package for a consumer communications application. 222-227 - David C. Keezer, K. E. Newman, John S. Davis:
Improved sensitivity for parallel test of substrate interconnections. 228-233 - Bruce C. Kim, David C. Keezer, Abhijit Chatterjee:
A high throughput test methodology for MCM substrates. 234-240
Session 10: Mixed-Signal Test Techniques
- Benoit Dufort, Gordon W. Roberts:
Increasing the performance of arbitrary waveform generators using sigma-delta coding techniques. 241-248 - Eric Rosenfeld, Solomon Max:
When "almost" is good enough: a fresh look at DSP clock rates. 249-253 - Luke S. L. Hsieh:
Reduction of errors due to source and meter in the nonlinearity test. 254-257 - S. Sasho, M. Shibata:
Multi-output one-digitizer measurement. 258-264
Session 11: Integrated Probe Card/Interface Solutions for Specific Test Applications
- Hervé Deshayes:
Cost of test reduction. 265-271 - Toshinori Ishii, Hideaki Yoshida:
Fine pitch (45 micron) P4 probing. 272-276 - Frederick L. Taber:
An introduction to area array probing. 277-281 - Jim Anderson:
Integrated probe card/interface solutions for specific test applications. 282-283
Session 12: Access and Test Approaches for Embedded Cores
- Erik Jan Marinissen, Robert G. J. Arendsen, Gerard Bos, Hans Dingemanse, Maurice Lousberg, Clemens Wouters:
A structured and scalable mechanism for test access to embedded reusable cores. 284-293 - Prab Varma, Sandeep Bhatia:
A structured test re-use methodology for core-based system chips. 294-302 - Lee Whetsel:
Core test connectivity, communication, and control. 303-312 - Janusz Rajski, Jerzy Tyszer:
Modular logic built-in self-test for IP cores. 313-321
Session 13: Test Synthesis
- Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu:
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. 322-330 - Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
TAO: regular expression based high-level testability analysis and optimization. 331-340 - Samy Makar:
A layout-based approach for ordering scan chain flip-flops. 341-347 - Mokhtar Hirech, James Beausang, Xinli Gu:
A new approach to scan chain reordering using physical design information. 348-355
Session 14: Transistor LeveL Test Techniques
- R. Dean Adams, Edmond S. Cooley, Patrick R. Hansen:
Quad DCVS dynamic logic fault modeling and testing. 356-362 - Peter Dahlgren:
Switch-level bridging fault simulation in the presence of feedbacks. 363-371 - Sandip Kundu:
GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification. 372-381
Session 15: Board and System Test
- Reuben Schrift:
Digital bus faults measuring techniques. 382-387 - John E. McDermid:
Limited access testing: IEEE 1149.4-instrumentation and methods. 388-395 - Frank W. Angelotti:
Generating interconnect models from prototype hardware. 396-403
Session 16: Recent Advances in BIST
- Charles E. Stroud, Sajitha Wijesuriya, Carter Hamilton, Miron Abramovici:
Built-in self-test of FPGA interconnect. 404-411 - Rainer Dorsch, Hans-Joachim Wunderlich:
Accumulator based deterministic BIST. 412-421 - Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik:
A BIST scheme for the detection of path-delay faults. 422-431
Session 17: Introduction to MEMS
- Kaigham J. Gabriel:
Microelectromechanical systems (MEMS) tutorial. 432-441 - Glenn F. LaVigne, Sam L. Miller:
A performance analysis system for MEMS using automated imaging methods. 442-447
Session 18: Advances in Embedded Core Test
- Joep Aerts, Erik Jan Marinissen:
Scan chain design for test time reduction in core-based ICs. 448-457 - Abhijit Jas, Nur A. Touba:
Test vector decompression via cyclical scan chains and its application to testing core-based designs. 458-464 - Makoto Sugihara, Hiroshi Date, Hiroto Yasuura:
A novel test methodology for core-based system LSIs and a testing time minimization problem. 465-472
Session 19: Microprocessor Testing
- Craig Hunter, Justin Gaither:
Design and implementation of the "G2" PowerPC 603e-embedded microprocessor core. 473-479 - Anjali Kinra, Aswin Mehta, Neal Smith, Jackie Mitchell, Fred Valente:
Diagnostic techniques for the UltraSPARC microprocessors. 480-486 - Dilip K. Bhavsar, David R. Akeson, Michael K. Gowan, Daniel B. Jackson:
Testability access of the high speed test features in the Alpha 21264 microprocessor. 487-495
Session 20: ATE Architectures: Cost, IDDQ and Mixed-Signal Issues
- Naveed Zaman, Antony Spilman:
Triggering and clocking architecture for mixed signal test. 496-499 - Ed Chang, David Cheung, Robert E. Huston, Jim Seaton, Gary Smith:
A scalable architecture for VLSI test. 500-506 - Robert Gage, Ben Brown:
The CAT-exact data transfer to DDS-generated clock domains in a single-chip modular solution. 507-513
Session 21: Concurrent Checking
- Steffen Tarnick, Albrecht P. Stroele:
Embedded self-testing checkers for low-cost arithmetic codes. 514-523 - Cecilia Metra, Michele Favalli, Bruno Riccò:
On-line detection of logic errors due to crosstalk, delay, and transient faults. 524-533 - Eduardo J. Peralías, Adoración Rueda, Juan A. Prieto, José L. Huertas:
DfT and on-line test of high-performance data converters: a practical case. 534-540
Session 22: MEMS Fault Modeling and Diagnosis
- A. Castillejo, D. Veychard, Salvador Mir, Jean-Michel Karam, Bernard Courtois:
Failure mechanisms and fault classes for CMOS-compatible microelectromechanical systems. 541-550 - Abhijeet Kolpekwar, Ronald D. Blanton, David Woodilla:
Failure modes for stiction in surface-micromachined MEMS. 551-556 - Abhijeet Kolpekwar, Chris S. Kellen, Ronald D. Blanton:
MEMS fault model generation using CARAMEL. 557-566
Session 23: Test Creation for Implicitly Burning Cores
- Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen:
Maximization of power dissipation under random excitation for burn-in testing. 567-576 - HyungWon Kim, John P. Hayes:
High-coverage ATPG for datapath circuits with unimplemented blocks. 577-586 - Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto:
Implicit test generation for behavioral VHDL models. 587-596
Session 24: Revolution and Evolution in Tester Software
- Dan Proskauer:
High quality, easy to use, on time ATE software Can it be done? 597-605 - John Oonk:
Leveraging new standards in ATE software. 606-611 - Craig Force, Tom Austin:
Testing the design: the evolution of test simulation. 612-621
Session 25: Practical ATPG
- Peter Wohl, John A. Waicukauski:
Extracting gate-level networks from simulation tables. 622-631 - Brion L. Keller, Kevin McCauley, Joseph Swenton, James Youngs:
ATPG in practical and non-traditional applications. 632-640 - Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Test generation in VLSI circuits for crosstalk noise. 641-650
Session 26: DFT Theory
- Priyank Kalla, Maciej J. Ciesielski:
A comprehensive approach to the partial scan problem using implicit state enumeration. 651-657 - Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai:
A novel combinational testability analysis by considering signal correlation. 658-667 - Yiorgos Makris, Alex Orailoglu:
DFT guidance through RTL test justification and propagation analysis. 668-677
Session 27: Mixed-Signal DFT
- Y. Xing:
Defect-oriented testing of mixed-signal ICs: some industrial experience. 678-687 - Ara Hajjar, Gordon W. Roberts:
A high speed and area efficient on-chip analog waveform extractor. 688-697 - Benoît R. Veillette, Gordon W. Roberts:
Stimulus generation for built-in self-test of charge-pump phase-locked loops. 698-707
Session 29: Microprocessor Test Tools
- Leland L. Day, Paul A. Ganfield, Dennis M. Rickert, Fred J. Ziegler:
Test methodology for a microprocessor with partial scan. 708-716 - Mary P. Kusko, Bryan J. Robbins, Thomas J. Snethen, Peilin Song, Thomas G. Foote, William V. Huott:
Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip. 717-726 - Young-Jun Kwon, Ben Mathew, Hong Hao:
FakeFault: a silicon debug software tool for microprocessor embedded memory arrays. 727-732
Session 30: Putting thE "Defect" in Defect Diagnosis
- Daniel R. Knebel, Pia N. Sanda, Moyra K. McManus, Jeffrey A. Kash, James C. Tsang, David P. Vallett, Leendert M. Huisman, Phil Nigh, Rick Rizzolo, Peilin Song, Franco Motika:
Diagnosis and characterization of timing-related defects by time-dependent light emission. 733-739 - Mario Paniccia, Travis M. Eiles, V. R. M. Rao, Wai Mun Yee:
Novel optical probing technique for flip chip packaged microprocessors. 740-747 - Jayashree Saxena, Kenneth M. Butler, Hari Balachandran, David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess:
On applying non-classical defect models to automated diagnosis. 748-757 - Yuan-Chieh Hsu, Sandeep K. Gupta:
A new path-oriented effect-cause methodology to diagnose delay failures. 758-767
Session 31: System Level Test Techniques and Processes
- Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
A fault injection environment for microprocessor-based boards. 768-773 - Chauchin Su, Shung-Won Jeng, Yue-Tsang Chen:
Boundary scan BIST methodology for reconfigurable systems. 774-783 - Susana Stoica:
A lifecycle approach to design validation is it necessary? Is it feasible? 784-792 - Moshe Ben-Bassat, Israel Beniaminy, David Joseph:
Can model-based and case-based expert systems operate together? 793-800
Session 32: The Need for Speed - Timing and Jitter Testing
- Leendert M. Huisman:
Correlations between path delays and the accuracy of performance prediction. 801-808 - Jerry Katz:
High speed testing-have the laws of physics finally caught up with us? 809-813 - Wajih Dalal, Daniel A. Rosenthal:
Measuring jitter of high speed data channels using undersampling techniques. 814-818 - Jan B. Wilstrup:
A method of serial data jitter analysis using one-shot time interval measurements. 819-823
Session 33: Vectors, Interface, Probes; ATE Issues in AT-Speed Test
- David C. Keezer, Q. Zhou:
Alternative interface methods for testing high speed bidirectional signals. 824-830 - Bob Hickling:
AVMTM a more usable way to execute vectors at double speed. 831-835 - Rajiv Pandey, Dan Higgins:
probe card-a solution for at-speed, high density, wafer probing. 836-842 - Wolfgang Mertin, Anton Leyk, Ulf Behnke, Volker Wittpahl:
Contactless gigahertz testing. 843-852
Session 34: Manufacturing Process Monitoring
- Dilip K. Bhavsar, Ugonna Echeruo, David R. Akeson, William J. Bowhill:
A highly testable and diagnosable fabrication process test chip. 853-861 - T. M. Mak, Debika Bhattacharya, Cheryl Prunty, Bob Roeder, Nermine Ramadan, F. Joel Ferguson, Jianlin Yu:
Cache RAM inductive fault analysis with fab defect modeling. 862-871 - Ivo Schanstra, Dharmajaya Lukita, Ad J. van de Goor, Kees Veelenturf, Paul J. van Wijnen:
Semiconductor manufacturing process monitoring using built-in self-test for embedded memories. 872-881
Session 35: Fault Detection and IDDQ
- Peter C. Maxwell, Jeff Rearick:
Estimation of defect-free IDDQ in submicron circuits using switch level simulation. 882-889 - Jonathan T.-Y. Chang, Edward J. McCluskey:
Detecting resistive shorts for CMOS domino circuits. 890-899 - Yukio Okuda, Isao Kubota, Masahiro Watanabe:
Defect level prediction for I_DDQ testing. 900-909
Session 36: On-Line Testing
- Ramesh Karri, Nilanjan Mukherjee:
Versatile BIST: an integrated approach to on-line/off-line BIST. 910-917 - Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantinos Halatsis:
R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique. 918-925 - Chouki Aktouf, Ghassan Al Hayek, Chantal Robach:
On-line testing of scalable signal processing architectures using a software test method. 926-933
Session 37: Creating Effective Test Sequences
- Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu:
A non-enumerative path delay fault simulator for sequential circuits. 934-943 - Ilker Hamzaoglu, Janak H. Patel:
Compact two-pattern test set generation for combinational and full scan circuits. 944-953 - Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy:
Static test sequence compaction based on segment reordering and accelerated vector restoration. 954-961
Session 38: Test Standards - Still Evolving
- Tony Taylor:
Standard test interface language (STIL), extending the standard. 962-970 - Peter Wohl, John A. Waicukauski:
Defining ATPG rules checking in STIL. 971-979 - Bulent I. Dervisoglu, Mike Ricchetti, William Eklow:
Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard. 980-989
Session 39: Design Validation and Diagnosis
- Jian Shen, Jacob A. Abraham:
Native mode functional test generation for processors with applications to self test and design validation. 990-999 - Morris Lin, James R. Armstrong, F. Gail Gray:
A goal tree based high-level test planning system for DSP real number models. 1000-1009 - Maisaa Khalil, Yves Le Traon, Chantal Robach:
Towards an automatic diagnosis for high-level design validation. 1010-1018
Session 40: Alternatives to IDDQ
- Claude Thibeault, Luc Boisvert:
Diagnosis method based on ΔIddq probabilistic signatures: experimental results. 1019-1026 - Bapiraju Vinnakota, Wanli Jiang, Dechang Sun:
Process-tolerant test with energy consumption ratio. 1027-1036 - Lan Zhao, D. M. H. Walker, Fabrizio Lombardi:
Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ. 1037-1046
Session 41: BIST Generator and Architectures
- Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer:
Automated synthesis of large phase shifters for built-in self-test. 1047-1056 - Gundolf Kiefer, Hans-Joachim Wunderlich:
Deterministic BIST with multiple scan chains. 1057-1064 - Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng:
An almost full-scan BIST solution-higher fault coverage and shorter test application time. 1065-1073
Session 42: New Ideas in Logic Diagnosis
- Irith Pomeranz, Sudhakar M. Reddy:
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination. 1074-1083 - David B. Lavo, Brian Chess, Tracy Larrabee, Ismed Hartanto:
Probabilistic mixed-model fault diagnosis. 1084-1093 - Vamsi Boppana, Masahiro Fujita:
Modeling the unknown! Towards model-independent fault and error diagnosis. 1094-1101
Session 43: Embedded Memories
- Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-based FPGA's: testing the LUT/RAM modules. 1102-1111 - Ilyoung Kim, Yervant Zorian, Goh Komoriya, Hai Pham, Frank P. Higgins, Jim L. Lewandowski:
Built in self repair for embedded high density SRAM. 1112-1119 - Roderick McConnell, Udo Möller, Detlev Richter:
How we test Siemens Embedded DRAM Cores. 1120-1125
Panel 1: Good Enough Quality - When is "Enough" Enough
- William R. Simpson:
Enough is enough already. 1127 - Bret A. Stewart:
Test: when is enough enough? 1128 - Susana Stoica:
How much testing is enough. 1129
Panel 2: Two Worlds Collide: Mixed Signal ASIC Testing
- Keith Baker:
Spice up your life: simulate mixed-signal ICs! 1131 - Mark Burns:
Testing mixed signal SOCs. 1132 - Ken Lanier:
When two worlds merge [test issues for system-level ICs]. 1133
Panel 3: Diagnostic War Stories: What Saved the Day? A Technique Debate
- Brian Chess:
Accounting for the unexpected: fault diagnosis out of the ivory tower. 1135 - Scott Davidson:
ASIC jeopardy-diagnosing without a FAB. 1136 - Vallluri R. Rao:
Design for diagnostics views and experiences. 1137 - Jayashree Saxena:
IC diagnosis: preventing wars and war stories. 1138
Panel 4: Scaling Deeper to Submicron: On-Line Testing to the Rescue
- Michael Nicolaidis:
Scaling Deeper to Submicron: On-Line Testing to the Rescue. 1139 - Michael Nicolaidis:
Design for soft-error robustness to rescue deep submicron scaling. 1140
Panel 5: The Road to System-on-Chip Test - It's a Matter of Cores - Is It?
- Todd E. Rockoff:
Learning to knit SOCs profitably. 1142 - Kamalesh N. Ruparel:
SOC test: the devil is in the details of integration/implementation. 1143 - Prab Varma:
System chip test: are we there yet? 1144
Panel 6: BIST vs. ATE: Which is Better, for Which IC Tests?
- Robert C. Aitken:
On-chip versus off-chip test: an artificial dichotomy. 1146 - Neil Kelly:
BIST vs. ATE for testing system-on-a-chip. 1147 - Stephen K. Sunter:
BIST vs. ATE: need a different vehicle? 1148 - Satoru Tanoi:
BIST: required for embedded DRAM. 1149
Panel 7: How Real is the new 1997 SIA Roadmap?
- Wayne M. Needham:
Just how real is the SIA roadmap. 1151 - Phil Nigh:
SIA Roadmap: test must not limit future technologies. 1152 - William R. Ortner:
How real is the new SIA roadmap for mixed-signal test equipment? 1153 - Todd E. Rockoff:
The rise and fall of the ATE industry. 1154 - Burnell G. West:
Functional ATE can meet the challenges. 1155
Panel 8: Academic Research: Power Plant or Ivory Tower?
- Kwang-Ting Cheng:
National Science Foundation Workshop on Future Research Directions in Testing of Electronic Circuits and Systems: executive summary of workshop report. 1157-1161
Panel 9: Flying Probers - A New Era in Loaded Board Fixtureless Test
- Jack Ferguson:
Flying probe test systems: capabilities for effective testing. 1163
Panel 10: Stuck-at Fault: The Fault Model of Choice for the Third Millennium!?
- Kenneth M. Butler:
The stuck-at fault: it ain't over 'til it's over. 1165 - Janak H. Patel:
Stuck-at fault: a fault model for the next millennium. 1166 - Jeff Rearick:
Buying time for the stuck-at fault model. 1167
Best Paper
- Anne E. Gattiker, Wojciech Maly:
Current signatures: application [to CMOS]. 1168-1177
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-25 20:49 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
