• 
  Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999. IEEE Computer Society 1999

Session 2: Mcm and Known-Good-Die Testing

• 
  David R. Lakin II, Adit D. Singh: Exploiting defect clustering to screen bare die for infant mortality failures: an experimental study. 23-30
• 
  Bruce C. Kim, Pinshan Jiang, Se Hyun Park: A probe scheduling algorithm for MCM substrates. 31-37
• 
  Alfredo Benso, Silvia Chiusano, Paolo Prinetto, Simone Giovannetti, Riccardo Mariani, Silvano Motto: Testing an MCM for high-energy physics experiments: a case study. 38-46

Session 3: Dynamic Current Testing

• 
  Bram Kruseman, Peter Janssen, Victor Zieren: Transient current testing of 0.25 /spl mu/m CMOS devices. 47-56
• 
  Wanli Jiang, Bapiraju Vinnakota: Statistical threshold formulation for dynamic I_dd test. 57-66
• 
  Amy Germida, Zheng Yan, James F. Plusquellic, Fidel Muradali: Defect detection using power supply transient signal analysis. 67-76

Session 4: Low Power And Diagnosis In Bist

• 
  Stefan Gerstendörfer, Hans-Joachim Wunderlich: Minimized power consumption for scan-based BIST. 77-84
• 
  Seongmoon Wang, Sandeep K. Gupta: LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation. 85-94
• 
  Jayabrata Ghosh-Dastidar, Debaleena Das, Nur A. Touba: Fault diagnosis in scan-based BIST using both time and space information. 95-102

Session 5: Volume Production Testing

• 
  Hari Balachandran, Jason Parker, Gordon Gammie, John W. Olson, Craig Force, Kenneth M. Butler, Sri Jandhyala: Expediting ramp-to-volume production. 103-112
• 
  Andrew C. Evans: Applications of semiconductor test economics, and multisite testing to lower cost of test. 113-123
• 
  Norma Barrett, Simon Martin, Chryssa Dislis: Test process optimization: closing the gap in the defect spectrum. 124-129

Session 6: Microprocessor Testing

• 
  Timothy J. Wood: The test and debug features of the AMD-K7 microprocessor. 130-136
• 
  Carol Pyron, Mike Alexander, James Golab, George Joos, Bruce Long, Robert F. Molyneaux, Rajesh Raina, Nandu Tendolkar: DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor. 137-146
• 
  Anjali Kinra: Towards reducing "functional only" fails for the UltraSPARC microprocessors. 147-154

Session 7: Board Test - Lecture Series

• 
  Stehpehn F. Scheiber: Breaking the complexity spiral in board test. 155-158
• 
  Adam W. Ley: The integration of boundary-scan test methods to a mixed-signal environment. 159-162
• 
  Thomas A. Ziaja: Using LSSD to test modules at the board level. 163-170

Session 8: Delay Testing

• 
  Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer: Switch-level delay test. 171-180
• 
  Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng: Delay testing considering power supply noise effects. 181-190
• 
  Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test generation for crosstalk-induced delay in integrated circuits. 191-200
• 
  Spyros Tragoudas: Accurate path delay fault coverage is feasible. 201-210

Session 9: Analog Test Methods

• 
  Clifford B. Cole, Thomas P. Warwick: High speed digital transceivers: A challenge for manufacturing. 211-215
• 
  Dino Ren Tao: A new approach to RF impedance test. 216-220
• 
  Jeongjin Roh, Jacob A. Abraham: Subband filtering scheme for analog and mixed-signal circuit testing. 221-229
• 
  Abdelhakim Khouas, Anne Derieux: Speed-up of high accuracy analog test stimulus optimization. 230-236

Session 10: Virtual And Real Test Software

• 
  J. J. O. Riordan: Design of a test simulation environment for test program development. 237-244
• 
  Mitsuo Matsumoto, Yoshiharu Ikeda: Automatic timing margin failure location analysis by CycleStretch method. 245-251
• 
  David A. Bonnett: Design for In-System Programming. 252-259

Session 11: DFT

• 
  Ramesh C. Tekumalla, Premachandran R. Menon: Robust testability of primitive faults using test points. 260-268
• 
  Eric MacDonald, Nur A. Touba: Delay testing of SOI circuits: Challenges with the history effect. 269-275
• 
  Mansour Shashaani, Manoj Sachdev: A DFT technique for high performance circuit testing. 276-285
• 
  Adit D. Singh, Egor S. Sogomonyan, Michael Gössel, Markus Seuring: Testability evaluation of sequential designs incorporating the multi-mode scannable memory element. 286-293

Session 12: Embedded Memories

• 
  Jeff Rearick: Practical scan test generation and application for embedded FIFOs. 294-300
• 
  Shigeru Nakahara, Keiichi Higeta, Masaki Kohno, Toshiaki Kawamura, Keizo Kakitani: Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm. 301-310
• 
  Dilip K. Bhavsar: An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264. 311-318

Session 13: Mems Fault Modeling and Test

• 
  Benoît Charlot, Salvador Mir, Érika F. Cota, Marcelo Lubaszewski, Bernard Courtois: Fault modeling of suspended thermal MEMS. 319-328
• 
  Tao Jiang, Ronald D. Blanton: Particulate failures for surface-micromachined MEMS. 329-337
• 
  Richard W. Beegle, Robert W. Brocato, Ronald W. Grant: IMEMS accelerometer testing-test laboratory development and usage. 338-347

Session 14: Industrial Applications of BIST

• 
  Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada: Low overhead test point insertion for scan-based BIST. 348-357
• 
  Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski: Logic BIST for large industrial designs: real issues and case studies. 358-367
• 
  Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski: Synthesis of pattern generators based on cellular automata with phase shifters. 368-377

Session 15: Production Wafer Test: Where the Probes Meet the Pads

• 
  Minh Quach, Rich Samuelson, David Shaw: Characterization and optimization of the production probing process. 378-387
• 
  Dean A. Gahagan: RF (gigahertz) ATE production testing on wafer: options and tradeoffs. 388-395
• 
  Jerry J. Broz, Reynaldo M. Rincon: Probe contact resistance variations during elevated temperature wafer test. 396-405

Session 16: Design Validation and Analysis for Evolving Technologies

• 
  Sezer Gören, F. Joel Ferguson: Checking sequence generation for asynchronous sequential elements. 406-413
• 
  Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann: Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. 414-420
• 
  Kyung Tek Lee, Jacob A. Abraham: Critical path identification and delay tests of dynamic circuits. 421-430

Session 17: Board Test: Interconnect Test

• 
  Benoit Nadeau-Dostie, Jean-Francois Cote, Harry Hulvershorn, Stephen Pateras: An embedded technique for at-speed interconnect testing. 431-438
• 
  Alex S. Biewenga, Henk D. L. Hollmann, Frans de Jong, Maurice Lousberg: Static component interconnect test technology (SCITT) a new technology for assembly testing. 439-448
• 
  Yuejian Wu, Paul Soong: Interconnect delay fault testing with IEEE 1149.1. 449-457

Session 18: Enhanced Test and Diagnosis of IC Process Defects

• 
  Hari Balachandran, Jason Parker, Daniel Shupp, Stephanie Butler, Kenneth M. Butler, Craig Force, Jason Smith: Correlation of logical failures to a suspect process step. 458-476
• 
  Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq: Optimal conditions for Boolean and current detection of floating gate faults. 477-486

Session 19: Embedded Core Test

• 
  Luis Basto, Asif Khan, Pete Hodakievic: Embedded X86 testing methodology. 487-492
• 
  Peter Harrod: Testing reusable IP-a case study. 493-498
• 
  Rochit Rajsuman: Testing a system-on-a-chip with embedded microprocessor. 499-508

Session 20: Issues in Tester Accuracy

• 
  Y. Cai, W. R. Ortner, C. T. Garrenton: Towards a standardized procedure for automatic test equipment timing accuracy evaluation. 509-517
• 
  Wajih Dalal, Song Miao: The value of tester accuracy. 518-523
• 
  Thomas P. Warwick, Jung Cho, Yi Cai, Bill Ortner: An accurate simulation model of the ATE test environment for very high speed devices. 524-531

Session 21: Mixed Signal BIST Techniques

• 
  Stephen K. Sunter, Aubin Roy: BIST for phase-locked loops in digital applications. 532-540
• 
  Benoit Provost, Edgar Sánchez-Sinencio: Auto-calibrating analog timer for on-chip testing. 541-548
• 
  Gloria Huertas, Diego Vázquez, Adoración Rueda, José L. Huertas: Effective oscillation-based test for application to a DTMF filter bank. 549-555

Session 22: Board Test: Practice Makes Perfect

• 
  Frans De Jong, Rob Raaijmakers: Static component interconnection test technology in practice. 556-565
• 
  David Rahe: The HASS development process. 566-576
• 
  Cherif Ahrikencheikh, Michael Spears: Limited access testing of analog circuits: handling tolerances. 577-586

Session 23: Fault Simulation from Bridges to RTL

• 
  R. Scott Fetherston, Imtiaz P. Shaik, Siyad C. Ma: A comparison of bridging fault simulation methods. 587-595
• 
  Vijay R. Sar-Dessai, D. M. H. Walker: Resistive bridge fault modeling, simulation and test generation. 596-605
• 
  Sitaran Yadavalli, Sudhakar M. Reddy: SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level. 606-615

Session 24: Practicing Embedded Core Test

• 
  Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel: Towards a standard for embedded core test: an example. 616-627
• 
  Robert C. Aitken, Fidel Muradali: Trends in SLI design and their effect on test. 628-637
• 
  Jos van Beers, Harry Van Herten: Test features of a core-based co-processor array for video applications. 638-647
• 
  Bozena Kaminska: Is Analog Fault Simulation a Key to Product Quality? Practical Considerations. 648

Session 25: (Panel) Is Analog Fault Simulation a Key to Product Quality? Practical Considerations

• 
  Eugene R. Atwood: Analog Fault Simulation: Need it? No. It is already done. 649
• 
  Craig Force: Analog Fault Simulation: Key to Product Quality, or a Foot in the Door. 650
• 
  Hosam Haggag: Closing The Gap Between Process Development and Mixed Signal Design and Testing. 651

Session 26: On-Line Testing Techniques

• 
  Cecilia Metra, Flavio Giovanelli, Mani Soma, Bruno Riccò: Self-checking scheme for very fast clocks' skew correction. 652-661
• 
  Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey: A design diversity metric and reliability analysis for redundant systems. 662-671
• 
  Chaohuang Zeng, Nirmal R. Saxena, Edward J. McCluskey: Finite state machine synthesis with concurrent error detection. 672-679

Session 27: System Test - Lecture Series

• 
  Simon Martin, Robert Bleck, Chryssa Dislis, Des Farren: The evolution of a system test process [for Motorola GSM products]. 680-688
• 
  Susana Stoica: System design verification tests - an overview. 689-697
• 
  David Williams: PC manufacturing test in a high volume environment. 698-704
• 
  Gordon D. Robinson: DFT, test lifecycles and the product lifecycle. 705-713

Session 28: Production I - Testing Beyond Single-Threshold Measurements

• 
  Claude Thibeault: An histogram based procedure for current testing of active defects. 714-723
• 
  Anthony C. Miller: I/sub DDQ/ testing in deep submicron integrated circuits. 724-729
• 
  Sri Jandhyala, Hari Balachandran, Anura P. Jayasumana: Clustering based techniques for I_DDQ testing. 730-737
• 
  Peter C. Maxwell, Pete O'Neill, Robert C. Aitken, Ronald Dudley, Neal Jaarsma, Minh Quach, Don Wiseman: Current ratios: a self-scaling technique for production I_DDQ testing. 738-746

Session 29: Testing Analog to Digital Converters

• 
  Turker Kuyel: Linearity testing issues of analog to digital converters. 747-756
• 
  Nico Csizmadia, Augustus J. E. M. Janssen: Estimating the integral non-linearity of A/D-converters via the frequency domain. 757-762
• 
  Solomon Max: Testing high speed high accuracy analog to digital converters embedded in systems on a chip. 763-771
• 
  Turker Kuyel, Haydar Bilhan: Relating linearity test results to design flaws of pipelined analog to digital converters. 772-779

Session 30: Issues in High-Speed Testing

• 
  Burnell G. West: Accuracy requirements in at-speed functional test. 780-787
• 
  Mike P. Li, Jan B. Wilstrup, Ross Jessen, Dennis Petrich: A new method for jitter decomposition through its distribution tail fitting. 788-794
• 
  Burnell G. West: At-speed structural test. 795-800
• 
  David C. Keezer, Q. Zhou: Test support processors for enhanced testability of high performance circuits. 801-809

Session 31: Test Methodology State of Practice and Case Studies

• 
  Magdy S. Abadir, Rajesh Raina: Design-for-test methodology for Motorola PowerPC microprocessors. 810-819
• 
  M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor: Testability of the Philips 80C51 micro-controller. 820-829
• 
  Li-C. Wang, Magdy S. Abadir: Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors. 830-838
• 
  Kenneth M. Butler: A study of test quality/tester scan memory trade-offs using the SEMATECH test methods data. 839-847

Session 32: System Test Methods from DFT to End of Live

• 
  Susana Stoica: Robust test methods applied to functional design verification. 848-857
• 
  Sandhya Seshadri, Michael S. Hsiao: An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques. 858-867
• 
  Lee A. Shombert, Danny C. Davis, Eric M. Bukata: The test requirements model (TeRM) communicating test information throughout the product life cycle. 868-876

Session 33: Design for Diagnostics

• 
  Richard H. Livengood, Donna Medeiros: Design for (physical) debug for silicon microsurgery and probing of flip-chip packaged integrated circuits. 877-882
• 
  William V. Huott, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Dennis Manzer, Pia Sanda, Steve Wilson, Yuen H. Chan, Antonio Pelella, Stanislav Polonsky: The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA). 883-891
• 
  Gert-Jan van Rootselaar, Bart Vermeulen: Silicon debug: scan chains alone are not enough. 892-902

Session 34: Test Synthesis

• 
  Han Bin Kim, Dong Sam Ha: A high-level BIST synthesis method based on a region-wise heuristic for an integer linear programming. 903-912
• 
  Alfred L. Crouch, Michael Mateja, Teresa L. McLaurin, John C. Potter, Dat Tran: The testability features of the 3rd generation ColdFire family of microprocessors. 913-922
• 
  Irith Pomeranz, Sudhakar M. Reddy: On achieving complete coverage of delay faults in full scan circuits using locally available lines. 923-931

Session 35: Mixed-Signal ATE Issues and Optical Probing

• 
  Keneth R. Wilsher, William K. Lo: Practical optical waveform probing of flip-chip CMOS devices. 932-939
• 
  Tagashi Kitagaki: Flexible ATE module with reconfigurable circuit and its application [to CMOS imager test]. 940-946
• 
  Koji Asami, Shinsuke Tajiri: A method to improve the performance of high-speed waveform digitizing. 947-954

Session 36: On-Line Testing for FPGAS and Processors

• 
  Sudip Chakrabarti, Abhijit Chatterjee: On-line fault detection in DSP circuits using extrapolated checksums with minimal test points. 955-963
• 
  Matthias Pflanz, Heinrich Theodor Vierhaus, F. Pompsch: An efficient on-line-test and back-up scheme for embedded processors. 964-972
• 
  Miron Abramovici, Charles E. Stroud, Carter Hamilton, Sajitha Wijesuriya, Vinay Verma: Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications. 973-982

Session 37: Memory Testing

• 
  A. J. van de Goor, Ivo Schanstra: Industrial evaluation of stress combinations for march tests applied to SRAMs. 983-992
• 
  Monica Lobetti Bodoni, Alessio Pricco, Alfredo Benso, Silvia Chiusano, Paolo Prinetto: An on-line BISTed SRAM IP core. 993-1000
• 
  Said Hamdioui, A. J. van de Goor: Port interference faults in two-port memories. 1001-1010

Session 38: Test Generation

• 
  Peter Wohl, John A. Waicukauski: Using Verilog simulation libraries for ATPG. 1011-1020
• 
  Kuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska: STAR-ATPG: a high speed test pattern generator for large scan designs. 1021-1030
• 
  Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer: Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies. 1031-1037

Session 39: Advanced Solution for SOC Test

• 
  Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian: HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs. 1038-1044
• 
  Hyungwon Kim, John P. Hayes: Delay fault testing of IP-based designs via symbolic path modeling. 1045-1054
• 
  Lee Whetsel: Addressable test ports an approach to testing embedded cores. 1055-1064

Session 40: Applying Diagnosis in a Production Test Environment

• 
  David B. Lavo, Tracy Larrabee, Jonathon E. Colburn: Eliminating the Ouija board: automatic thresholds and probabilistic I_DDQ diagnosis. 1065-1072
• 
  Peilin Song, Franco Motika, Daniel R. Knebel, Rick Rizzolo, Mary P. Kusko, Julie Lee, Moyra K. McManus: Diagnostic techniques for the IBM S/390 600 MHz G5 microprocessor. 1073-1082
• 
  Yun Shao, Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz: The effects of test compaction on fault diagnosis. 1083-1089

Session 41: Time-to-Market - Lecture Series

• 
  Jim Johnson: Is DFT right for you? 1090-1097
• 
  Jon Turino: Design for test and time to market-friends or foes. 1098-1101
• 
  Bulent I. Dervisoglu: Design for testability: it is time to deliver it for Time-to-Market. 1102-1111
• 
  Mahesh A. Iyer: High Time For High Level ATPG. 1112

Panel 1: High Time for High-Level ATPG

• 
  Wu-Tung Cheng: High time for high level ATPG. 1113
• 
  Scott Davidson: Changing our Path to High Level ATPG. 1114
• 
  Rohit Kapur: High level ATPG is important and is on its way! 1115-1116
• 
  Christos A. Papachristou: High Time for Higher Level BIST. 1117
• 
  Matteo Sonza Reorda: High-level ATPG: a real topic or an academic amusement? 1118
• 
  Wolfgang Roethig: High-level ATPG for Early Power Analysis. 1119-1120
• 
  Keith Baker: SIA Roadmaps: Sunset Boulevard for l_DDQ. 1121
• 
  Jeffrey L. Roehr: Thin Gate Oxide Reliability. 1122

Panel 4: Thin Gate Oxide Reliability

• 
  E. James Prendergast: Applying lessons learned from TDDB testing. 1123-1124
• 
  Scott Davidson: ITC'99 Benchmark Circuits - Preliminary Results. 1125

Panel 6: ITC'99 Benchmark Circuits - Preliminary Results

• 
  Chouki Aktouf: Scan Insertion at the Behavioral Level. 1126
• 
  Mario H. Konijnenburg, Hans van der Linden, Jeroen Geuzebroek: Benchmarking DAT with the ITC'99 ATPG Benchmarks. 1127
• 
  Sudhakar M. Reddy: Application of Tools Developed at the University of Iowa to ITC Benchmarks. 1128
• 
  Jean François Santucci, Christophe Paoli: High level test bench generation using software engineering concepts. 1129
• 
  Raghuram S. Tapuri: Automatic Functional Test Generation - A Reality. 1130
• 
  Vishwani D. Agrawal: Panel: Increasing test coverage in a VLSI desgin course. 1131

Panel 7: Increasing Test Coverage in VLSI Design

• 
  Jacob A. Abraham: Position Statement: Increasing Test Coverage in a VLSI Design Course. 1132
• 
  Michael L. Bushnell: Increasing Test Coverage in a VLSI Design Course. 1133
• 
  John Harrington: VLSI design 101 - The test module. 1134
• 
  Michel Robert: Increasing test coverage in a VLSI design course. 1135
• 
  Mani Soma: Panel Statement: Increasing test coverage in a VLSI design course. 1136
• 
  Wayne Wolf: Position Statement: Testing in a VLSI Design Course. 1137
• 
  Frans de Jong: SCITT: Back to Basics in Mass Production Testing. 1138

Panel 8: SCITT: Back to Basics in Mass Production Testing

• 
  Frank W. Angelotti: SCITT: Bringing DRAMs Into the Test Fold. 1139
• 
  Steffen Hellmold: Static Component Interconnection Test Technology (SCITT). 1140
• 
  David M. Wu: DFT is all I can afford, who cares about Design for Yield or Design for Reliability! 1141-1142

Panel 9: DIFT is all I Can Afford, Who Vares About Design for Yield or Design for Reliability!

• 
  Robert C. Aitken: It Makes Sense to Combine DFT and DFR/DFY. 1143
• 
  R. Scott Fetherston: DFT, DFY, DFR: Who Cares? 1144
• 
  James A. Monzel: DFT, DFY, and DFR; Which One(s) Do You Worry About? 1145
• 
  D. M. H. Walker: Design for Yield and Reliability is MORE Important Than DFT. 1146
• 
  David M. Wu: "DFY and DFR are more important than DFT". 1147
• 
  Peter Wohl: Output in still, input in still. 1148

Panel 10: Output in STIL, Input in STIL

• 
  Nathan Biggs: STIL: the device-oriented database for the test development lifecycle. 1149
• 
  Brion L. Keller: Using STIL to describe embedded core test requirements. 1150
• 
  Marc Loranger: Is there a STIL for mixed signal testing? 1151

ITC'98 Best Paper

• 
  Phil Nigh, David P. Vallett, Atul Patel, Jason Wright, Franco Motika, Donato O. Forlenza, Ray Kurtulik, Wendy Chong: Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment. 1152-1161