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ORCID9th MTV 2008: Austin, TX, USA
- Ninth International Workshop on Microprocessor Test and Verification, MTV 2008, Austin, Texas, USA, 8-10 December 2008. IEEE Computer Society 2008, ISBN 978-0-7695-3581-4
Multi-core Verification
- Joseph W. Lyles Jr.:
Vertical Reuse Strategy for Testbench Components Supporting Memory Consistency Checking of an SMP-Capable AMD64 Processor. 3-6 - Alan Hunter, Andrew Piziali, Avi Ziv, Kelly Larson, Shankar Hemmady:
Ensuring Functional Closure of a Multi-core SoC through Verification Planning, Implementation and Execution. 7-13 - William W. Collier:
Testing Memory Models. 14-17 - Alexander Weiss, Christian Hochberger:
A New Methodology for the Test of SoCs and for Analyzing Elusive Failures. 18-23
Sequential Equivalence Checking Paradigm
- Mark H. Nodine:
Preparing Rearchitected Designs for Sequential Equivalence Checking. 27-32 - Chia-Ling Lynn Chang, Charles H.-P. Wen
:
Mining Unreachable Cross-Timeframe State-Pairs for Bounded Sequential Equivalence Checking. 33-38 - Nathan Sheeley, Nicolas Pena, Irfan Waheed, Mark H. Nodine:
Enhancing Sequential LEC Using a Cumulative Verification Methodology. 39-42
Debug
- Sandip Ray:
Abstraction as a Practical Debugging Tool. 45-48 - Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton:
BackSpace: Moving Towards Reality. 49-54
Power Management Verification
- Ryan Ritesh M. Pinto:
Power Management Verification - An Evolving Discipline. 57-60 - Sumit Ahuja, Deepak Mathaikutty, Sandeep K. Shukla:
Applying Verification Collaterals for Accurate Power Estimation. 61-66 - Bhanu Kapoor, J. Marc Edwards, Shankar Hemmady, Shireesh Verma, Kaushik Roy:
Tutorial: SoC Power Management Verification and Testing Issues. 67-72
Advanced Verification Methodologies
- Thinh Ngo:
Enhancing Verification Efficiency via Dynamically Focused, Selective and Intrusive Transactions. 75-80 - Kana Murale, Scot Hildebrandt, Per Bojsen, Alfonso Urzua:
AMD64 Processor Front-End Verification (at Unit-Level Testbench) with Instruction Set Simulator. 81-87 - Ulrich Kühne, Daniel Große, Rolf Drechsler:
Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow. 88-93 - Y. B. Liao, P. Li, A. W. Ruan, Y. W. Wang, W. C. Li, W. Li:
Hierarchy Communication Channel in Transaction-Level Hardware/Software Co-emulation System. 94-99
Delay Fault Testing
- Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda:
A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores. 103-108
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