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ORCID1. PACS 2000: Cambridge, MA, USA
- Babak Falsafi, T. N. Vijaykumar:
Power-Aware Computer Systems, First International Workshop, PACS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers. Lecture Notes in Computer Science 2008, Springer 2001, ISBN 3-540-42329-X
Power-Aware Microarchitectural/Circuit Techniques
- Flavius Gruian
:
System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors. 1-12 - Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa, Lei He:
Ramp Up/Down Functional Unit to Reduce Step Power. 13-24 - Alper Buyuktosunoglu, Stanley Schuster, David M. Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi:
An Adaptive Issue Queue for Reduced Power at High Performance. 25-39
Application/Compiler Optimizations
- Paul Marchal, Chun Wong, Aggeliki S. Prayati, Nathalie Cossement, Francky Catthoor, Rudy Lauwereins, Diederik Verkest, Hugo De Man:
Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform. 40-50 - Jeongseon Euh, Wayne P. Burleson:
Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering. 51-64 - Chung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao:
Compiler-Directed Dynamic Frequency and Voltage Scheduling. 65-81
Exploiting IPC/Memory Slack
- Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, Rae McLellan:
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power. 82-96 - Roberto Maro, Yu Bai, R. Iris Bahar:
Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors. 97-111
Power/Performance Models and Tools
- Ashutosh S. Dhodapkar, Chee How Lim, George Cai, W. Robert Daasch:
TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator. 112-125 - David M. Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose:
Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor. 126-136 - Soraya Ghiasi, Dirk Grunwald:
A Comparison of Two Architectural Power Models. 137-152
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