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ORCIDReConFig 2005: Puebla City, Mexico
- 2005 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2005, Puebla City, Mexico, September 28-30, 2005. IEEE Computer Society 2005, ISBN 0-7695-2456-7
Image Processing
- Marco Aurelio Nuño-Maganda
, Miguel O. Arias-Estrada:
Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling. - Miguel Angel Sánchez Martínez, Adriano De Luca Pennacchia:
An image comparison circuit design. - Griselda Saldaña, Miguel Arias-Estrada:
FPGA-based customizable systolic architecture for image processing applications.
Arithmetic
- Sabel Mercurio Hernández Rodríguez, Francisco Rodríguez-Henríquez:
An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add method. - Alejandro Ordaz-Moreno, René de Jesús Romero-Troncoso, Jose Alberto Vite-Frias:
Hardware signal processing unit for one-dimensional variable-length discrete wavelet transform.
Architecture
- Vijay Pandya, Shawki Areibi, Medhat Moussa:
A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays. - Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Juan Suardíaz Muro, Eduardo I. Boemo:
Rapid prototyping of a self-timed ALU with FPGAs. - Juan José Raygoza-Panduro, Susana Ortega-Cisneros, Eduardo I. Boemo:
FPGA implementation of a synchronous and self-timed neuroprocessor.
Reconfiguration
- Sebastian Lange, Martin Middendorf:
On the design of two-level reconfigurable architectures. - Javier Castillo, Pablo Huerta, Víctor López, José Ignacio Martínez:
A secure self-reconfiguring architecture based on open-source hardware. - Patrick Rocke, John Maher, Fearghal Morgan:
Platform for intrinsic evolution of analogue neural networks.
Tools
- David B. Thomas, Wayne Luk:
High quality uniform random number generation for massively parallel simulations in FPGA. - André L. S. Braga, Carlos H. Llanos, Mauricio Ayala-Rincón, Ricardo P. Jacobi:
VANNGen: a flexible CAD tool for hardware implementation of artificial neural networks. - Oliver Pell, Wayne Luk:
Quartz: a framework for correct and efficient reconfigurable design.
Physical design
- Martin Zabel, Steffen Köhler, Martin Zimmerling, Thomas B. Preußer, Rainer G. Spallek:
Design space exploration of coarse-grain reconfigurable DSPs. - Annie Avakian, Iyad Ouaiss:
Optimizing register binding in FPGAs using simulated annealing.
Architecture 2
- José Francisco Martínez Trinidad, René Cumplido-Parra, Claudia Feregrino Uribe:
An FPGA-based parallel sorting architecture for the Burrows Wheeler transform.
Tools 2
- Corey J. Milliord, Carthik A. Sharma, Ronald F. DeMara:
Dynamic voting schemes to enhance evolutionary repair in reconfigurable logic devices. - Fearghal Morgan, Patrick Rocke, Martin O'Halloran:
Applied VHDL training methodology, EDA framework and hardware implementation platform.
Short Papers
- Ossi Laakkonen, Hannu Sarén, Kimmo Rauma, Olli Pyrhönen:
FPGA implementation of DSVPWM modulator. - Kimmo Rauma, Julius Luukko, Torsti Härkönen, Ilkka Pajari, Olli Pyrhönen:
A novel FPGA implementation of a welding control using a new bus architecture. - Joaquín García, René Cumplido-Parra:
On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004. - Snaider L. Carrillo, Agenor Z. Polo, Mario P. Esmeral:
Design and implementation of an embedded microprocessor compatible with IL language in accordance to the norm IEC 61131-3. - Jose Alberto Vite-Frias, René de Jesús Romero-Troncoso, Alejandro Ordaz-Moreno:
VHDL core for 1024-point radix-4 FFT computation. - Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation. - Mario Alberto Garcia Martinez, Rubén Posada-Gómez, Guillermo Morales-Luna, Francisco Rodríguez-Henríquez:
FPGA implementation of an efficient multiplier over finite fields GF(2m). - Guillermo Marcus, Juan Arturo Nolazco-Flores:
An FPGA-based coprocessor for the SPHINX speech recognition system: early experiences. - Alfonso Ávila, Rolando Santoyo-Rincón, Sergio Omar Martinez-Chapa, Graciano Dieck-Assad:
Hardware/software implementation of a discrete cosine transform algorithm using SystemC.
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