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ORCIDVLSI 2003: Las Vegas, Nevada, USA
- Hamid R. Arabnia, Laurence Tianruo Yang:
Proceedings of the International Conference on VLSI, VLSI '03, June 23 - 26, 2003, Las Vegas, Nevada, USA. CSREA Press 2003, ISBN 1-932415-10-6
Digital Signal Processing
- Fred L. Anderson IV, José G. Delgado-Frias:
A Reconfigurable Switch for a DSP Array. VLSI 2003: 3-6 - Christian Panis, Gunther Laure, Wolfgang Lazian, Herbert Grünbacher, Jari Nurmi:
A Branch File for a Configurable DSP Core. VLSI 2003: 7-12 - Hoon Na, Dae-Gwon Jeong:
MPEG-4 HVXC Real-Time Implementation on Floating Point DSP. VLSI 2003: 13-20
Reconfigurable Computing
- Mitchell J. Myjak, José G. Delgado-Frias:
A Two-Level Reconfigurable Architecture for Digital Signal Processing. VLSI 2003: 21-27 - Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown:
Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. VLSI 2003: 28-33 - X. Zhang, Gabriel Dragffy, Anthony G. Pipe:
Bio-Inspired Reconfigurable Architecture for Reliable Systems. VLSI 2003: 34-40 - Deshanand P. Singh, Stephen Dean Brown:
An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. VLSI 2003: 41-50
Fault Tolerance
- Hussain Al-Asaad, Alireza Sarvi:
Fault Tolerance for Multiprocessor Systems Via Time Redundant Task Scheduling. VLSI 2003: 51-57 - Daniel R. Blum, José G. Delgado-Frias:
A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP Processor. VLSI 2003: 58-64 - Jie Han, Pieter Jonker:
A Study on Fault-Tolerant Circuits Using Redundancy. VLSI 2003: 65-69 - Robert Chun, Linda Yang:
Reuse of Firmware Tests in System-On-Chip Design Verification. VLSI 2003: 70-78
Low Power Design
- Jiyi Gu, Majid Ahmadi, William C. Miller:
A Low-Voltage Low-Power Digital-Audio Sigma-Delta Modulator in 0.18-µm CMOS. VLSI 2003: 79-82 - Anilkumar Patro, Ashish Mishra:
Lower Power Processor Design Issues. VLSI 2003: 83-86 - Jaime Ramírez-Angulo, Shanta Thoutam, Gladys Omayra Ducoudray, Ramón González Carvajal:
A New Power Efficient Fully Differential Low-Voltage Two Stage OP-AMP Architecture. VLSI 2003: 87-91 - Naresh Sarwabhotla, Arthi Kothandaraman:
A Power-Efficient Level Converter Design For Multi-Supply Voltage CMOS Analog Integrated Circuits. VLSI 2003: 92-96 - Arifur Rahman:
Models for Full-Chip Power Dissipation in Field Programmable Gate Arrays and the Impact of Subthreshold Leakage Current. VLSI 2003: 97-106
Noise Reduction and Crosstalk
- Thomas Eschbach, Wolfgang Günther, Bernd Becker:
Cross Reduction for Orthogonal Circuit Visualization. VLSI 2003: 107-113 - Janet Meiling Wang, Pinhong Chen, Omar Hafiz:
Switching Windows Computation in Presence of Crosstalk Noise. VLSI 2003: 114-118 - Nathaniel Bird, Ethan S. Miller, Paul J. Pfeiffer, Srinivasa Vemuru:
Channel Routing with Crosstalk Consideration. VLSI 2003: 119-124 - Sumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi:
Energy Efficient and Noise-Tolerant XOR-XNOR Circuit Design. VLSI 2003: 125-130
Circuits and Systems
- Manfred Schimmler, Bertil Schmidt, Hans-Werner Lang, Sven Heithecker:
An Area-Efficient Bit-Serial Integer Multiplier. VLSI 2003: 131-137 - Ali Telli, Simsek Demir, Murat Askar:
Planar Spiral Inductor Modeling for RFIC Design. VLSI 2003: 138-142 - Scott C. Smith:
Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy. VLSI 2003: 143-149 - Volnei A. Pedroni:
High-Resolution WTA-MAX Circuit for Large Networks. VLSI 2003: 150-154 - Adnan M. Lokhandwala, Sudip K. Mazumder:
A Novel Smart Power ASIC (SPIC) for Integrated Control of Cascaded Power Converters. VLSI 2003: 155-161 - Youngsoo Kim, Janghong Yoon, Sungok Kim:
An Improved Circuit Design for Parallel Sequence Generation. VLSI 2003: 162-165 - Khia-Ho Chang, Bah-Hwee Gwee, Joseph Sylvester Chang:
A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register File. VLSI 2003: 166-172 - Yil Suk Yang, Jongdae Kim, Tae Moon Roh, Dae Wood Lee, Sung-Ku Kwon, Il Yong Park, Byoung Gon Yu:
Level Shifter Circuit Having Dual Outputs for FPD Gate Driver. VLSI 2003: 173-177 - Satish K. Bandapati, Scott C. Smith:
Design and Characterization of NULL Convention Arithmetic Logic Units. VLSI 2003: 178-184 - Kang Hyeon Rhee:
A Study on the 8bit Pipeline RISC Processor. VLSI 2003: 185-189 - Evandro de Araújo Jardini, Dilvan de Abreu Moreira:
Multithreaded parallel VLSI Leaf Cell Generator Using Agents 2. VLSI 2003: 190-196
Quantum Computing
- Noboru Watanabe:
Foundation of Quantum Capacity. VLSI 2003: 197-202 - Satoshi Ikeda, Izumi Kubo, Masafumi Yamashita:
Reducing the Hitting and the Cover Times of Random Walks on Finite Graphs by Local Topological Information. VLSI 2003: 203-207 - Luigi Accardi, Masanori Ohya:
A Stochastic Limit Approach to the SAT Problem. VLSI 2003: 208-216
Testing and Verification
- Amardeep Singh:
Quantum Search Algorithm for Automated Test Pattern Generation in VLSI Testing. VLSI 2003: 217-223 - L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti, Sivaprakasam Suresh:
On-Line Location of Multiple Faults in LUT Based Reconfigurable Systems. VLSI 2003: 224-232
Devices and Circuits
- Yiming Li, Shao-Ming Yu, Hsiao-Mei Lu:
Intelligent Device Parameter Extraction for Nanoscale MOSFETs Era. VLSI 2003: 233-239 - J. K. Kim, S. H. Won, Ki-Seok Chung, H. D. Cho, T. W. Kang, T. S. Nam, C. S. Kang, C. H. Yi, D. S. Kim:
Properties of A1/BaTa2O6/GaN MIS Structure. VLSI 2003: 240-243 - Shih-Ching Lo, Jyun-Hwei Tsai, Jer-Ming Hsu, Yiming Li:
Quantum Mechanical Gate Current Simulation in MOSFETs with Ultrathin Oxides. VLSI 2003: 244-250 - Jam Wem Lee, Yiming Li, Howard Tang:
Silicide Optimization for Electrostatic Discharge Protection Devices in Sub-100 nm CMOS Circuit Design. VLSI 2003: 251-260
High-Level Design
- Sankalp Kallakuri, Alex Doboli, Simona Doboli:
Applying Stochastic Modeling to Bus Arbitration for Network-On-Chip Systems. VLSI 2003: 261-265 - Keun Soo Yim, Kern Koh, Hyokyung Bahn:
A Compressed Page Management Scheme for NAND-Type Flash Memory. VLSI 2003: 266-271 - Ling Wang, Yingtao Jiang, Henry Selvaraj:
Scheduling and Optimal Voltage Selection with Multiple Supply Voltages under Resource Constraints. VLSI 2003: 272-278 - Seung Wook Lee, Jong Tae Kim:
Universal Reed-Solomon Decoder Using Hardware/Software Co-Design Method. VLSI 2003: 279-284
Complexity Issues
- Manfred Schimmler, Viktor Bunimov:
A Simple Circuit to Reduce the Search Range for Large Prime Numbers. VLSI 2003: 285-291 - Rita M. Hare, Bryant A. Julstrom:
A Genetic Algorithm for Restricted Cases of the Rectilinear Steiner Problem with Obstacles. VLSI 2003: 292-297 - Todd W. Neller, David C. Hettlinger:
Learning Annealing Schedules for Channel Routing. VLSI 2003: 298-302 - Andris Ambainis, Uldis Barbans, Agnese Belousova, Aleksandrs Belovs, Ilze Dzelme, Girts Folkmanis, Rusins Freivalds, Peteris Ledins, Rihards Opmanis, Agnis Skuskovniks:
Size of Quantum Versus Deterministic Finite Automata. VLSI 2003: 303-308 - Lelde Lace, Rusins Freivalds:
Lower Bounds for Query Complexity of Some Graph Problems. VLSI 2003: 309-316
Security Application
- Hirotsuga Kajisaki, Takakazu Kurokawa:
SEBSW-2: SEcret-Key Block Cipher SWitcher. VLSI 2003: 317-323 - Gene Eu Jan, Chiou-Min Shen, Shao-Wei Leu, Cheng-Hung Li:
The Design and Analysis of an Elliptic Curve Cryptosystem. VLSI 2003: 324-328 - Gene Eu Jan, Lokar J. Y. Lin, W. R. Liou, Y. Y. Chen:
The Design and Implementation of a 2048-Bit RSA Encryption/Decryption Chip. VLSI 2003: 329-338
Applications, Algorithms + Novel Designs
- Mitra Mirhassani, Majid Ahmadi, William C. Miller:
A Feed-Forward Time-Multiplexed Neural Network with Mixed-Signal Neuron-Synapse Arrays. VLSI 2003: 339-344 - Jaime Ramírez-Angulo, Chandrika Durbha, Gladys Omayra Ducoudray, Ramón González Carvajal:
Highly Linear Wide Input Range CMOS OTA Architectures Operating in Subthreshold and Strong Inversion. VLSI 2003: 345-350 - Bhupen P. Zaveri:
Phase Coincidence Technique for Frequency Difference Measurement. VLSI 2003: 351-355 - Jae-Young Yi, Yong-Hui Lee, Cheon-Hee Yi:
PEDE (Plasma Edge Damage Effect) Curing by Various Heat Treatment. VLSI 2003: 356-360 - Vishal Verma, Himanshu Thapliyal:
A High Speed Efficient N x N Bit Multiplier Based on Ancient Indian Vedic Mathematics. VLSI 2003: 361-365 - YunKyung Lee, YoungSu Park:
High Speed, Small Area AES Block Cipher Coprocessor Design for USIM Card. VLSI 2003: 366-372
Late Papers and Post-Conference Papers
- Srinivasa Vemuru:
Simultaneous Switching Noise Estimation Including the Effects of the Driving Transistor Gate-Source Capacitance. VLSI 2003: 373-378 - Scott F. Smith:
The Advanced Encryption Standard on an Asynchronous Shared-Memory Multiprocessor. VLSI 2003: 379-381 - Suleyman Tosun, Hakduran Koc, Nazanin Mansouri:
Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs. VLSI 2003: 382-
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