Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDVLSI-SoC 2012: Santa Cruz, CA, USA
- Srinivas Katkoori, Matthew R. Guthaus, Ayse K. Coskun, Andreas Burg, Ricardo Reis:
20th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012. IEEE 2012, ISBN 978-1-4673-2657-5
Electronics for Bio-systems
- Matthew R. Guthaus:
Welcome from the general chair. - Le Zheng, Sangho Shin, Sung-Mo Steve Kang:
Design of a neural stimulator system with closed-loop charge cancellation. 1-6 - Kenneth O'Neal, Daniel T. Grissom, Philip Brisk
:
Force-Directed List Scheduling for Digital Microfluidic Biochips. 7-11 - Surya Sharma, Trond Ytterdal:
Low noise front-end amplifier design for medical ultrasound imaging applications. 12-17
Networks on Chip
- Mingyang Zhu, Jinho Lee, Kiyoung Choi:
An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidth. 18-23 - Anelise Kologeski, Caroline Concatto, Fernanda Lima Kastensmidt, Luigi Carro:
ATARDS: An adaptive fault-tolerant strategy to cope with massive defects in Network-on-Chip interconnections. 24-29 - Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini:
3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory. 30-35
Transistor Level Digital Circuits
- Stefano Pietri, Chris Dao, Juxiang Ren, Jehoda Refaeli, Alfredo Olmos:
Safety oriented automotive MCU power management. 36-40 - Farhad Alibeygi Parsan, Scott C. Smith:
CMOS implementation of static threshold gates with hysteresis: A new approach. 41-45
Analog & Mixed Signal Design
- Sohail Asghar, Rocío del Río, José M. de la Rosa:
A 0.2-to-2MHz BW, 50-to-86dB SNDR, 16-to-22mW flexible 4th-order ΣΔ modulator with DC-to-44MHz tunable center frequency in 1.2-V 90-nm CMOS. 47-52 - Neil Di Spigna, Daniel Schinke, Srikant Jayanti, Veena Misra, Paul D. Franzon:
A novel double floating-gate unified memory device. 53-58
Digital Circuits and Systems I
- Haven Blake Skinner, Xuchu Hu, Matthew R. Guthaus:
Harmonic resonant clocking. 59-64 - Andreas Minwegen, Dominik Auras, Gerd Ascheid:
A multimode decision-directed channel estimation ASIC for MIMO-OFDM. 65-70 - Christian Benkeser, Christoph Roth, Qiuting Huang:
Turbo decoder design for high code rates. 71-75
Memristive Computing
- Fernando Corinto, Alon Ascoli, Marco Gilli:
A novel elementary memristive system. 76-81 - Advait Madhavan, Dmitri B. Strukov:
Mapping of image and network processing tasks on high-throughput CMOL FPGA circuits. 82-87 - Ligang Gao, Fabien Alibart, Dmitri B. Strukov:
Analog-input analog-weight dot-product operation with Ag/a-Si/Pt memristive devices. 88-93 - Pierre-Emmanuel Gaillardon, Davide Sacchetto, Shashikanth Bobba, Yusuf Leblebici, Giovanni De Micheli:
GMS: Generic memristive structure for non-volatile FPGAs. 94-98 - Ravi Patel, Eby G. Friedman:
Arithmetic encoding for memristive multi-bit storage. 99-104
Digital Circuits and Systems II
- Pierre Greisen, Richard Emler, Michael Schaffner, Simon Heinzle, Frank K. Gürkaynak:
A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOS. 105-110 - Qiuling Zhu, Larry T. Pileggi, Franz Franchetti:
Cost-effective smart memory implementation for parallel backprojection in computed tomography. 111-116 - Cristiano Thiele, Bruno Boessio Vizzotto, André L. M. Martinez, Vagner Santos Da Rosa, Sergio Bampi:
A low-cost and high efficiency entropy encoder architecture for H.264/AVC. 117-122 - Michael Muehlberghuber, Christoph Keller, Norbert Felber, Christian Pendl:
100 Gbit/s authenticated encryption based on quantum key distribution. 123-128
Verification and Fault Tolerance
- Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
On the optimized generation of Software-Based Self-Test programs for VLIW processors. 129-134 - Sebastian Steinhorst, Lars Hedrich:
Equivalence checking of nonlinear analog circuits for hierarchical AMS System Verification. 135-140 - Shilpa Pendyala, Srinivas Katkoori:
Interval arithmetic based input vector control for RTL subthreshold leakage minimization. 141-146
Multi-core and embedded SoC
- Radu David, Paul Bogdan, Radu Marculescu:
Dynamic power management for multicores: Case study using the intel SCC. 147-152 - Zhibin Xiao, Bevan M. Baas:
A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architecture. 153-158 - Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg:
TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing. 159-164
Open Source Tools and Methodologies for Research
- Niket K. Choudhary, Brandon H. Dwiel, Eric Rotenberg:
A physical design study of fabscalar-generated superscalar cores. 165-170 - Anton Tsepurov, Gunter Bartsch, Rainer Dorsch, Maksim Jenihhin, Jaan Raik, Valentin Tihhomirov:
A scalable model based RTL framework zamiaCAD for static analysis. 171-176 - Daniel T. Grissom, Kenneth O'Neal, Benjamin Preciado, Hiral Patel, Robert Doherty, Nick Liao, Philip Brisk:
A digital microfluidic biochip synthesis framework. 177-182 - Gregory G. Faust, Runjie Zhang, Kevin Skadron, Mircea R. Stan, Brett H. Meyer:
ArchFP: Rapid prototyping of pre-RTL floorplans. 183-188
Design for Reliability
- Hamid Mahmoodi:
Reliability enhancement of power gating transistor under time dependent dielectric breakdown. 189-194 - Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba:
Using asymmetric layer repair capability to reduce the cost of yield enhancement in 3D stacked memories. 195-200 - Tasreen Charania, Pierce Chuang, Ajoy Opal, Manoj Sachdev:
Suppression of on-chip power supply noise generated by a 64-bit static logic ALU block. 201-206 - Seokjoong Kim, Matthew R. Guthaus:
Dynamic voltage scaling for SEU-tolerance in low-power memories. 207-212
FPGA Design and Optimization
- Krishna Chaitanya Nunna, Farhad Mehdipour, Masayoshi Yoshimura, Kazuaki J. Murakami:
Methodology for early estimation of hierarchical routing resources in 3D FPGAs. 213-218 - Rajsaktish Sankaranarayanan, Matthew R. Guthaus:
A single-VDD ultra-low energy sub-threshold FPGA. 219-224 - Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Evaluation of fault tolerant technique based on homogeneous FPGA architecture. 225-230
Power and Temperature Management
- Bin Wu, Peng Li:
Load-aware stochastic feedback control for DVFS with tight performance guarantee. 231-236 - Haroon Mahmood, Massimo Poncino, Mirko Loghi, Enrico Macii:
Aging-aware caches with graceful degradation of performance. 237-242 - Jie Meng, Fulya Kaplan, Ming-yu Hsieh, Ayse K. Coskun:
Topology-aware reliability optimization for multiprocessor systems. 243-246
Poster
- Andy Motten, Luc Claesen, Yun Pan:
Trinocular disparity processor using a hierarchic classification structure. 247-250 - Anupam Chattopadhyay, Goutam Paul:
Exploring security-performance trade-offs during hardware accelerator design of stream cipher RC4. 251-254 - Christina Gimmler-Dumont, Christian Brehm, Norbert Wehn:
Reliability study on system memories of an iterative MIMO-BICM system. 255-258 - Hamed Sajjadi Kia, Cristinel Ababei:
A new reliability evaluation methodology and its application to network-on-chip routers. 259-262 - Jongpil Jung, Kyungsu Kang, Jae-Jin Lee, Youngjun Yoon, Chong-Min Kyung:
Cost-effective TSV redundancy configuration. 263-266 - Victor Frederico Silva, Cantidio de Oliveira Fontes, Flávio Rech Wagner:
The impact of synchronization in message passing while scaling multi-core MPSoC systems. 267-270 - Chirag Ravishankar, Andrew A. Kennings, Jason Helge Anderson:
FPGA power reduction by guarded evaluation considering physical information. 271-274 - Jaspal Singh Shah, David Nairn, Manoj Sachdev:
A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm. 275-278 - Sandro Belfanti, Christian Benkeser, Karim Badawi, Qiuting Huang, Andreas Burg:
Successive interference cancellation for 3G downlink: Algorithm and VLSI architecture. 279-282 - Kyungsu Kang, Luca Benini, Giovanni De Micheli:
A high-throughput and low-latency interconnection network for multi-core Clusters with 3-D stacked L2 tightly-coupled data memory. 283-286 - Avijit Dutta:
Low cost adjacent double error correcting code with complete elimination of miscorrection within a dispersion window for Multiple Bit Upset tolerant memory. 287-290 - Takeshi Matsumoto, Shohei Ono, Masahiro Fujita:
An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence. 291-294 - Abhishek Guar, Hamid Mahmoodi:
Impact of technology scaling on performance of domino logic in nano-scale CMOS. 295-298 - Hamed Tabkhi, Gunar Schirner:
ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors. 299-302 - Ilias Pappas, Vasilios Kalenteridis, Stylianos Siskos, Spiridon Vlassis:
A complete over-current/short-circuit protection system for Low-Drop Out regulators. 303-306 - Ignatius Bezzam, Shoba Krishnan, Chakravarthy Mathiazhagan:
Low power SoCs with resonant dynamic logic using inductors for energy recovery. 307-310 - K. T. Hafeez, Ashudeb Dutta, Shiv Govind Singh:
Efficient adaptive switch design for charge pumps in micro-scale energy harvesting. 311-314
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-25 20:49 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
