Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID7th VLSI Design 1994: Calcutta, India
- Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994. IEEE Computer Society 1994, ISBN 0-8186-4990-9
Keynote Address
- Joseph B. Costello:
On the Brink of a New Era in VLSI Design. VLSI Design 1994: 3
Plenary Session Invited Talk
- Pallab K. Chatterjee:
Gigachip Technology and the Signal Processing Revolution. VLSI Design 1994: 4
1. High Level Synthesis 1
- Ahmed Hemani, Börje Karlsson, Mats Fredriksson, Kurt Nordqvist, Björn Fjellborg:
Application of High-Level Synthesis in an Industrial Project. 5-10 - Pradip K. Jha, Champaka Ramachandran, Nikil D. Dutt
, Fadi J. Kurdahi:
An Empirical Study on the Effects of Physical Design in High-Level Synthesis. 11-16 - Samit Chaudhuri, Robert A. Walker:
ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis. 17-20 - A. R. Naseer, M. Balakrishnan, Anshul Kumar:
FAST: FPGA Targeted RTL Structure Synthesis Technique. 21-24 - David J. Kolson, Nikil D. Dutt, Alexandru Nicolau:
Ultra Fine-Grain Template-Driven Synthesis. 25-28
2. Parallel Algorithms
- Sharad C. Seth, Lee Gowen, Matt Payne, Don Sylwester:
Logic Simulation Using an Asynchronous Parallel Discrete-Event Simulation Model on a SIMD Machine. 29-32 - Abhaya Asthana, Mike Laznovsky, Boyd Mathews:
SEMU: A Parallel Processing System for Timing Simulation of Digital CMOS VLSI Circuits. 33-38 - C. V. Ramamoorthy, Vikram Vij:
CM-SIM: A Parallel Circuit Simulator on a Distributed Memory Multiprocessor. 39-44 - Prathima Agrawal, Sanjay Goil, Sally Liu, John A. Trotter:
Parallel Model Evaluation for Circuit Simulation on the PACE Multiprocessor. 45-48 - Dharmavani Bhagavathi, Stephan Olariu, James L. Schwing, Jingyuan Zhang:
Time- and Cost-Optimal Parallel Algorithms for the Dominance and Visibility Graphs. 49-52
3. Analog Circuits
- Dundar Dumlugol, Don Webber, Rajeev Madhavan:
Analog Modeling Using Event-Driven HDL's. 53-56 - Qingjian Yu, Omar Wing:
A SPICE Model of RLGC Transmission Line with Error Control. 57-60 - Naim Ben-Hamida, Bozena Kaminska:
Multiple Fault Testing in Analog Circuits. 61-66 - Bapiraju Vinnakota, Ramesh Harjani:
The Design of Analog Self-Checking Circuits. 67-70 - Joydeep Ghosh, Patrick LaCour, Spence Jackson:
OTA Based Neural Network Architectures with On-Chip Tuning of Synapses. 71-76
4. Digital Signal Processing
- Debabrata Ghosh, S. K. Nandy, K. Parthasarathy:
TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. 77-82 - Keshab K. Parhi:
Calculation of Minimum Number of Registers in Arbitrary Life Time Chart. 83-86 - Arup K. Bhattacharya, Syed S. Haider:
A VLSI Architecture of an Inverse Discrete Cosine Transform. 87-90 - Heonchul Park, Viktor K. Prasanna:
A Fast Algorithm for Performing Vector Quantization and its VLSI Implementation. 91-94 - Debabrata Ghosh, Shamik Sural, S. K. Nandy:
A 600MHz Half-Bit Level Pipelined Multiplier Macrocell. 95-100
5. Design for Testability
- Shang-E Tai, Debashis Bhattacharya:
A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow Graph. 101-106 - C. P. Ravikumar, Haroon Rasheed:
Simulated Annealing for Target-Oriented Scan. 107-112 - Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal:
A Test Function Architecture for Interconnected Finite State Machines. 113-116 - Md. Abdul Mottalib, P. Dasgupta:
A Bist PLA Design for High Fault Coverage and Testing by an Interleavingly Crosspoint Counting. 117-122 - Harry Hengster, Rolf Drechsler, Bernd Becker:
Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model. 123-126
6. Routing
- Keumog Ahn, Sartaj Sahni:
Flipping Modules to Improve Circuit Performance and Routability. 127-132 - Jens Lienig, Krishnaiyan Thulasiraman:
A New Genetic Algorithm for the Channel Routing Problem. 133-136 - Jim E. Crenshaw, Spyros Tragoudas, Naveed A. Sherwani:
High Performance Over-the-Cell Routing. 137-142 - Siddharth Bhingarde, Rafay Khawaja, Anand Panyam, Naveed A. Sherwani:
Over-the-Cell Routing Algorithms for Industrial Cell Models. 143-148 - Paul Molitor, Uwe Sparmann, Dorothea Wagner:
Two-Layer Wiring with Pin Preassignments is Easier if the Power Supply Nets are Already Generated. 149-154
7. High Level Synthesis 2
- Pradip K. Jha, Nikil D. Dutt:
Rapid Technology Projection for High-Level Synthesis. 155-158 - Yinghua Min, Yutang Zhou, Zhongcheng Li, Cheng Ye, Yuqi Pan:
Behavioral Design and Prototyping of a Fail-Safe System. 159-162 - Ashutosh Mujumdar, Minjoong Rim, Rajiv Jain, Renato De Leone:
BINET: An Algorithm for Solving the Binding Problem. 163-168 - Sukumar Nandi, Vamsi Boppana, Parimal Pal Chaudhuri:
A CAD Tool for Design of On-Chip Store & Generate Scheme. 169-174 - Neeta Ganguly, Vijay Pitchumani:
HSIM1 and HSIM2: Object Oriented Algorithms for VHDL Simulation. 175-178
8. CMOS Testing
- Sreejit Chakravarty, Sivaprakasam Suresh:
IDDQ Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits. 179-182 - Suntae Hwang, Rochit Rajsuman, Scott Davidson:
IDDQ Detection of CMOS Bridging Faults by Stuck-At Fault Tests. 183-186 - Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana, Carol Q. Tong:
The Effect of Built-In Current Sensors (BICS) on Operational and Test Performance. 187-190 - S. M. Aziz, W. A. J. Waller:
On Testability of Differential Split-Level CMOS Circuits. 191-196 - K. Biswas, S. Rai:
Testable Realizations of CMOS Combinatorial Circuits for Voltage and Current Testing. 197-202
9. Layout
- Reena Agarwal, Indranil Sengupta:
On the Synthesis of Gate Matrix Layout. 203-206 - Tanuj Bagchi, Sajal K. Das:
An Efficient Hybrid Heuristic for the Gate Matrix Layout Problem in VLSI Design. 207-210 - Henrik Esbensen, Pinaki Mazumder:
SAGA: A Unification of the Genetic Algorithm with Simulated Annealing and its Application to Macro-Cell Placement. 211-214 - Cyrus Bamji, Jonathan Allen:
GLOVE: A Graph-Based Layout Verifier. 215-220 - Kalapi Roy-Neogi, Bingzhong Guan, Carl Sechen:
A Sea-of-Gates Style FPGA Placement Algorithm. 221-224
10. FPGA
- G. N. Rathna, S. K. Nandy, K. Parthasarathy:
A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs. 225-228 - Abhijit Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal:
High Speed Digital Filtering on SRAM-Based FPGAs. 229-232 - Mahesh Mehendale:
Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures. 233-236 - Amit Chowdhary, Dinesh Bhatia:
Detailed Routing of Multi-Terminal Nets in FPGAs. 237-242
11. ASIC and Logic Design
- Hemant Kanakia:
A Switch-Memory Chip for Packet Switching at Gigabits per Second. 243-246 - V. Keshava Murthy, K. Madhu Kumar, Mallikarjun B. Vani, D. Jagadish Kumar, C. S. Mohan, B. S. Prasanna:
A 2Kx1K Space Switch ASIC for Use in Digital Exchanges. 247-250 - Arunita Jaekel, Subir Bandyopadhyay, Abhijit Sengupta:
Laout Influenced Factorization of Boolean Functions. 251-254 - Irith Pomeranz, Sudhakar M. Reddy:
On Determining Symmetries in Inputs of Logic Circuits. 255-260
12. Low Power VLSI
- Anantha P. Chandrakasan, Mani B. Srivastava, Robert W. Brodersen:
Energy Efficient Programmable Computation. 261-264 - Abhijit Chatterjee, Rabindra K. Roy:
Synthesis of Low Power Linear DSP Circuits Using Activity Metrics. 265-270 - Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal:
Power Constraint Scheduling of Tests. 271-274
13. Algorithms/Architectures
- Indradeep Ghosh, Bandana Majumdar:
Design of an Application Specific VLSI Chip for Image Rotation. 275-278 - P. Pal Chowdhury, R. Barua:
Cellular Automata Based VLSI Architecture for Computing Multiplication and Inverses in GF (2m). 279-282 - Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri:
Architecture for VLSI Design of CA Based Byte Error Correcting Code Decoders. 283-286 - Feng-Ming Yang, Stefan Wolter, Rainer Laur:
VLSI Architecture for HDTV Motion Estimation Based on Block-Matching Algorithm. 287-290 - Mario Kovac, N. Ranganathan:
ACE: A VLSI Chip for Galois Field GF (2m) Based Exponentiation. 291-296
14. Testing/Fault Simulation
- Dong Xiang, Daozheng Wei:
An Optimal Design for Parallel Test Generation Based on Circuit Partitioning. 297-300 - Mohamed Jamoussi, Bozena Kaminska:
Data Path Testability Evaluation via Functional Testability Measures. 301-306 - P. R. Suresh Kumar, James Jacob, Mandyam-Komar Srinivas, Vishwani D. Agrawal:
An Improved Deductive Fault Simulator. 307-310 - Sunil R. Das, Wen-Ben Jone, Amiya Nayak, Ian Choi:
On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition. 311-314 - Mahesh A. Iyer, Miron Abramovici:
Low-Cost Redundancy Identification for Combinatorial Circuits. 315-318
15. VLSI Technology
- G. Hari Rama Krishna, Nirmal B. Chakrabarti, Swapna Banerjee:
Finite Element Analysis of SIGe npn HBT. 319-322 - Srikanth Natarajan, Debapriya Sahu, Sattam Dasgupta:
nOHM - A Multi-Process Device Synthesis Tool for Lateral DMOS Structures. 323-327 - S. K. Lahiri, M. K. Das, A. Das Gupta, I. Manna:
3D Effects in VLSI/ULSI MOSFETs: A Novel Analytical Approach to Model Threshold Voltage. 328-332 - M. K. Kidambi, Akhilesh Tyagi, Mohammed R. Madani, Magdy A. Bayoumi:
Parameterized Modeling of Open-Circuit Critical Volume for Three-Dimensional Defects in VLSI Processing. 333-338 - A. Bandyopadhyay, P. R. Verma, A. B. Bhattacharyya, M. J. Zarabi:
LATCHSIM - A Lath-Up Simulator in VLSI CAD Environment for CMOS and BiCMOS Circuits. 339-342
16. VLSI/WSI Arrays
- V. K. Anuradha, V. Visvanathan:
A CORDIC Based Programmable DXT Processor Array. 343-348 - Dinesh Bhatia, Ramesh Rajagopalan, Srinivas Katkoori:
Hierarchical Reconfiguration of VLSI/WSI Arrays. 349-352 - Emmanuel Casseau, Dominique Degrugillier:
A Linear Systolic Array for LU Decomposition. 353-358 - Manoj Franklin, Kewal K. Saluja:
An Algorithm to Test Reconfigured RAMs. 359-364 - Kanad Ghose, V. Anand Dharmaraj:
Response Pipelined CAM Chips: The First Generation and Beyond. 365-368
17. FSM Synthesis
- Mahesh Mehendale, Biswadip Mitra:
An Integrated Approach to State Assignment and Sequential Element Selection for FSM Synthesis. 369-372 - Chunduri Rama Mohan, Partha Pratim Chakrabarti:
A New Approach to Synthesis of PLA-Based FSM's. 373-378 - José Monteiro, James H. Kukula, Srinivas Devadas, Horácio C. Neto:
Bitwise Encoding of Finite State Machines. 379-382 - Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan:
Synthesis of Initializable Asynchronous Circuits. 383-388 - I. Chakrabarti, Dipankar Sarkar:
Mechanical Identification of Inductive Properties During Verification of Finite State Machines. 389-394
18. Design Space Exploration
- Pallab Dasgupta, Prasenjit Mitra, P. P. Chakrabarti, S. C. De Sarkar:
Multiobjective Search in VLSI Design. 395-400 - James Sienicki, Michael L. Bushnell, Sandip Parikh:
Graphical Methodology Language for CAD Frameworks. 401-406 - Santonu Sarkar, Anupam Basu:
An Object Oriented Environment for Modeling and Synthesis of Hardware Circuits. 407-412 - Mourad B. Takla, Donald W. Bouldin, Daniel B. Koch:
Early Exploration of the Multi-Dimensional VLSI Design Space. 413-416 - Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell:
Verification of Circuits Described in VHDL through Extraction of Design Intent. 417-420
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-22 20:01 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
