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ORCID27th VLSI Design 2014: Munbai, India
- 2014 27th International Conference on VLSI Design, VLSID 2014, and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-2513-1
Tutorials
- Anil Kumar Gupta, Anand Singh, Vineeta Yadav:
Tutorial T1: Ambient Intelligence through Internets-of-Things - An Application Development Approach. 1 - Parmesh Ramanathan:
Tutorial T2A: Scheduling Issues in Embedded Real-Time Systems. 2 - Barun Kumar De, Anupam Chattopadhyay, Ansuman Banerjee:
Tutorial T2B: Cost / Application / Time to Market Driven SoC Design and Manufacturing Strategy. 3-4 - Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula:
Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices. 5-6 - Sridhar Rangarajan, Pinaki Chakrabarti, Sourav Sahais, Ayan Datta, Adarsh Subramanya:
Tutorial T3B: Engineering Change Order (ECO) Phase Challenges and Methodologies for High Performance Design. 7-8 - Mohammad Tehranipoor, Domenic Forte:
Tutorial T4: All You Need to Know about Hardware Trojans and Counterfeit ICs. 9-10 - Krishnendu Chakrabarty, Tsung-Yi Ho
:
Tutorial T5: Microfluidic Biochips: Connecting VLSI and Embedded Systems to the Life Sciences. 11-12 - Nagendra Krishnapura:
Tutorial T6A: Pedagogy of Negative Feedback Circuits. 13 - Swaroop Ghosh:
Tutorial T6B: Embedded Memory Design for Future Technologies: Challenges and Solutions. 14-15 - Santanu Chattopadhyay:
Tutorial T7A: Techniques for Network-on-Chip (NoC) Design and Test. 16-17 - Joycee Mekie, Sneha N. Ved:
Tutorial T7B: Network on Chips - The Journey Overview. 18 - B. Ravi Kishore, B. Kameswara Rao:
Tutorial T8A: Realization of RF Front-End for a Cognitive Radio. 19
Session A1: 3D Test
- Spencer K. Millican, Kewal K. Saluja:
A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits. 20-25 - Eshan Singh:
Analytical Modeling of 3D Stacked IC Yield from Wafer to Wafer Stacking with Radial Defect Clustering. 26-31 - Nima Aghaee, Zebo Peng, Petru Eles:
Process-Variation Aware Multi-temperature Test Scheduling. 32-37 - Subhendu Roy, David Z. Pan:
Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown. 38-43
Session A2: SAT Application
- Mehdi Dehbashi, Görschwin Fey:
Debug Automation for Synchronization Bugs at RTL. 44-49 - Kun Bian, D. M. H. Walker, Sunil P. Khatri:
Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation. 50-55 - Alexander Czutro, Sudhakar M. Reddy, Ilia Polian, Bernd Becker:
SAT-Based Test Pattern Generation with Improved Dynamic Compaction. 56-61 - Matthias Sauer, Sven Reimer, Sudhakar M. Reddy, Bernd Becker:
Efficient SAT-Based Circuit Initialization for Larger Designs. 62-67
Session A3: Design Verification
- David Sheridan, Lingyi Liu, Hyungsul Kim, Shobha Vasudevan:
A Coverage Guided Mining Approach for Automatic Generation of Succinct Assertions. 68-73 - Pradeep Kumar Nalla, Raj Kumar Gajavelly, Hari Mony, Jason Baumgartner, Robert Kanzelman:
Effective Liveness Verification Using a Transformation-Based Framework. 74-79 - M. H. Haghbayan, Bijan Alizadeh, Payman Behnam, Saeed Safari:
Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism. 80-85 - Yinlei Yu, Pramod Subramanyan, Nestan Tsiskaridze, Sharad Malik:
All-SAT Using Minimal Blocking Clauses. 86-91
Session A4: Test Generation
- Spencer K. Millican, Parameswaran Ramanathan, Kewal K. Saluja:
CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities. 92-97 - Sharada Jha, Kameshwar Chandrasekar, Weixin Wu, Ramesh Sharma, Sanjay Sengupta, Sudhakar M. Reddy:
A Cube-Aware Compaction Method for Scan ATPG. 98-103 - Xiaoke Qin, Prabhat Mishra:
Scalable Test Generation by Interleaving Concrete and Symbolic Execution. 104-109 - Rahul Shukla, Phong Loi, Ken Pham, Arie Margulis, Kathy Yang, Nagesh Tamarapalli:
Application of Test-View Modeling to Hierarchical ATPG. 110-115
Session A5: Reliable Circuits
- Nandakishor Yadav, Sunil Dutt, G. K. Sharma:
A New Sensitivity-Driven Process Variation Aware Self-Repairing Low-Power SRAM Design. 116-121 - Jayaram Natarajan, Sahil Kapoor, Debesh Bhatta, Abhijit Chatterjee, Adit D. Singh:
Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity Completion Sensing with Backup Error Resilience. 122-127 - B. Naveen Kumar Reddy, M. Chandra Sekhar, Sreehari Veeramachaneni, M. B. Srinivas:
A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units. 128-132 - Ravi Kanth Uppu, Ravi Tej Uppu, Adit D. Singh, Ilia Polian:
Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. 133-138
Session A6: Memory
- Sudhanshu Khanna, Satyanand Nalam, Benton H. Calhoun:
Pipelined Non-strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories. 139-144 - K. R. Viveka, Bharadwaj Amrutur:
Energy Efficient Memory Decoder Design for Ultra-low Voltage Systems. 145-149 - Prashant Dubey, Gaurav Ahuja, Vaibhav Verma, Sanjay Kumar Yadav, Amit Khanuja:
A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist. 150-155 - Ignatius Bezzam, Shoba Krishnan:
Minimizing Power and Skew in VLSI-SoC Clocking with Pulsed Resonance Driven De-skewing Latches. 156-161
Session B1: Real-Time Systems
- Mingsong Chen, Fan Gu, Lei Zhou, Geguang Pu, Xiao Liu:
Efficient Two-Phase Approaches for Branch-and-Bound Style Resource Constrained Scheduling. 162-167 - Hsiang-Kuo Tang, Parmesh Ramanathan, Katherine Morrow:
Inserting Placeholder Slack to Improve Run-Time Scheduling of Non-preemptible Real-Time Tasks in Heterogeneous Systems. 168-173 - Santu Sardar, K. Ananda Babu:
Hardware Implementation of Real-Time, High Performance, RCE-NN Based Face Recognition System. 174-179
Session B2: Embedded Platform
- Marcelo Trindade Rebonatto, Fabiano Passuelo Hessel, Luiz Eduardo Schardong Spalding:
EME Electric Supervision Embedded on Gas Panel with Microshock Dangerousness Degree. 180-185 - Sudhakar Singamala, Mandfed Brandl, Sandeep Vernekar, Veereshbabu Vulligadala, Ravikumar Adusumalli, Vijay Ele:
Design of AFE and PWM Drive for Lithium-Ion Battery Management System for HEV/EV System. 186-191 - E. M. T. Sirisha, T. Sridevi, D. Thirugnana Murthy:
Process Disturbance Analyzer for Nuclear Reactors. 192-197 - Manoj Kumar Misra, N. Sridhar, D. Thirugnana Murthy:
Design and Implementation of Safety Logic with Fine Impulse Test System for a Nuclear Reactor Shutdown System. 198-203
Session B3: Architectures
- Rance Rodrigues, Israel Koren, Sandip Kundu:
Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core. 204-209 - Arun Joseph, Nagu R. Dhanwada:
Process Synchronization in Multi-core Systems Using On-Chip Memories. 210-215 - Xiaoke Qin, Prabhat Mishra:
TECS: Temperature- and Energy-Constrained Scheduling for Multicore Systems. 216-221 - Jyoti Gajrani, Pooja Mazumdar, Sampreet A. Sharma, Bernard Menezes:
Challenges in Implementing Cache-Based Side Channel Attacks on Modern Processors. 222-227
Session B4: Network-on-Chip
- César A. M. Marcon, Ramon Fernandes, Rodrigo Cataldo, Fernando Grando, Thais Webber, Ana Benso, Leticia B. Poehls:
Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization. 228-233 - Tejasi Pimpalkhute, Sudeep Pasricha:
NoC Scheduling for Improved Application-Aware and Memory-Aware Transfers in Multi-core Systems. 234-239 - Manoj Kumar, Vijay Laxmi, Manoj Singh Gaur, Seok-Bum Ko, Mark Zwolinski:
CARM: Congestion Adaptive Routing Method for On Chip Networks. 240-245 - Bhanu Pratap Singh, Arunprasath Shankar, Francis G. Wolff, Daniel J. Weyer, Christos A. Papachristou, Bhanu Negi:
Knowledge-Guided Methodology for Third-Party Soft IP Analysis. 246-251
Session B5: MPSoCs
- César A. M. Marcon, Thais Webber, Leticia B. Poehls, Igor K. Pinotti:
Pre-mapping Algorithm for Heterogeneous MPSoCs. 252-257 - Farhad Merchant, Anupam Chattopadhyay, Ganesh Garga, S. K. Nandy, Ranjani Narayan, Nandhini Gopalan:
Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR). 258-263 - Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja:
Temperature Minimization Using Power Redistribution in Embedded Systems. 264-269 - Nishit Ashok Kapadia, Sudeep Pasricha:
Process Variation Aware Synthesis of Application-Specific MPSoCs to Maximize Yield. 270-275
Session B6: Embedded Systems
- Wim Meeus, Tom Vander Aa, Praveen Raghavan, Dirk Stroobandt:
Hard versus Soft Software Defined Radio. 276-281 - Vikas S. Vij, Raghu Prasad Gudla, Kenneth S. Stevens:
Interfacing Synchronous and Asynchronous Domains for Open Core Protocol. 282-287 - Brajendra Kumar Singh, Kemal E. Tepe, Mohammed A. S. Khalid:
Control Mechanism to Solve False Blocking Problem at MAC Layer in Wireless Sensor Networks. 288-293 - Amit Pande, Shaxun Chen, Prasant Mohapatra, Gaurav Pande:
Architecture for Blocking Detection in Wireless Video Source Authentication. 294-299
Session C1: FPGA
- Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan:
A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm. 300-305 - B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan:
Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs. 306-311 - Burhan Khurshid, Roohie Naaz Mir:
A Hardware Intensive Approach for Efficient Implementation of Numerical Integration for FPGA Platforms. 312-317 - Amin Ghasemazar, Mehran Goli, Ali Afzali-Kusha:
Embedded Complex Floating Point Hardware Accelerator. 318-323
Session C2: Low-Power Design
- Arnab Raha, Hrishikesh Jayakumar, Vijay Raghunathan:
A Power Efficient Video Encoder Using Reconfigurable Approximate Arithmetic Units. 324-329 - Hrishikesh Jayakumar, Arnab Raha, Vijay Raghunathan:
QUICKRECALL: A Low Overhead HW/SW Approach for Enabling Computations across Power Cycles in Transiently Powered Computers. 330-335 - Parastoo Kamranfar, Ali Shahabi, Ghazaleh Vazhbakht, Zainalabedin Navabi:
Configurable Systolic Matrix Multiplication. 336-341 - Neel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti:
ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. 342-347
Session C3: Digital Design
- Anand D. Darji, Saurabh Shukla, S. N. Merchant, Arun N. Chandorkar:
Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform. 348-352 - Narayan V. Sugur, Saroja V. Siddamal, Samba Sivam Vemala:
Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology. 353-358 - Sundarrajan Rangachari, Jaiganesh Balakrishnan, Nitin Chandrachoodan:
Scalable Low Power FFT/IFFT Architecture with Dynamic Bit Width Configurability. 359-364 - Ch. Santosh Varma, Syed Ershad Ahmed, M. B. Srinivas:
A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter. 365-368
Session C4: Physical Design
- Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
Global Routing Using Monotone Staircases with Minimal Bends. 369-374 - Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu:
Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire. 375-380 - Raghavan Kumar, Siva Nishok Dhanuskodi, Sandip Kundu:
On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions. 381-386 - Partha Pratim Saha, Tuhina Samanta:
Obstacle Avoiding Rectilinear Clock Tree Construction with Skew Minimization. 387-392 - Matthias Beste, Saman Kiamehr, Mehdi Baradaran Tahoori:
Layout-Aware Delay Variation Optimization for CNTFET-Based Circuits. 393-398
Session C5: Modeling and Simulation
- Ayan Paul, Chaitanya Kshirsagar, Sachin S. Sapatnekar, Steven J. Koester, Chris H. Kim:
Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations. 399-404 - Neha Sharan, Santanu Mahapatra:
Small Signal Nonquasi-static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry. 405-410 - Parmanand Singh, Vivek Asthana, Radhakrishnan Sithanandam, Anand Bulusu, Sudeb Dasgupta:
Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor. 411-414 - Michael Meixner, Tobias G. Noll:
Statistical Modeling of Glitching Effects in Estimation of Dynamic Power Consumption. 415-420
Session C6: Modeling and Analysis
- Anupam Dutta, Saurabh Sirohi, Ethirajan Tamilmani, Harshit Agarwal, Yogesh Singh Chauhan, Richard Q. Williams:
BSIM6 - Benchmarking the Next-Generation MOSFET Model for RF Applications. 421-426 - Amrita Kumari, Subindu Kumar:
Analysis of Nanoscale Strained-Si/SiGe MOSFETs including Source/Drain Series Resistance through a Multi-iterative Technique. 427-432 - Manodipan Sahoo, Prasun Ghosal, Hafizur Rahaman:
An ABCD Parameter Based Modeling and Analysis of Crosstalk Induced Effects in Multiwalled Carbon Nanotube Bundle Interconnects. 433-438 - Mukta Singh Parihar, Abhinav Kranti:
Performance Optimization and Parameter Sensitivity Analysis of Ultra Low Power Junctionless MOSFETs. 439-443
Session D1: RF Circuits
- Rajesh Cheeranthodi, Santhosh Madhavan, Umesh K. Shukla, Giri Rangan:
Improvements to Negative-C Compensation Based Amplifiers for Broadband Applications. 444-449 - Sushrant Monga, Shouri Chatterjee:
An Adaptive Inductorless Continuous Time Equalizer for Gigabit Links in 0.13 um CMOS. 450-454 - Sivaramakrishna Rudrapati, Shalabh Gupta:
On Dependence of Amplitude Noise versus Offset Frequency in LC Oscillators. 455-459 - Arunkumar Salimath, Pradeep Karamcheti, Achintya Halder:
A 1 V, Sub-mW CMOS LNA for Low-Power 1 GHz Wide-Band Wireless Applications. 460-465
Session D2: LP Circuits
- Sanjay Kumar Wadhwa, Jaideep Banerjee, Rakesh Kumar Gupta:
Low Power Single Amplifier Voltage Regulator. 466-469 - Matthew Morrison, Nagarajan Ranganathan:
Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS. 470-475 - Sourindra Chaudhuri, Niraj K. Jha:
FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage. 476-482 - Lokesh Siddhu, Amit Mishra, Virendra Singh:
Operand Isolation with Reduced Overhead for Low Power Datapath Design. 483-488 - Mohammad Yousef Zarei, Mahdi Mosaffa, Siamak Mohammadi:
High-Speed, Low-Power Quasi Delay Insensitive Handshake Circuits Based on FinFET Technology. 489-494
Session D3: MEMS/Biochips
- Pramod Kaddi, Basireddy Karunakar Reddy, Shiv Govind Singh:
Active Cooling Technique for Efficient Heat Mitigation in 3D-ICs. 495-498 - A. V. S. S. Prasad, K. P. Venkatesh, Rudra Pratap, Navakanta Bhat:
Improved Design Methodology for the Development of Electrically Actuated MEMS Structures. 499-503 - Sukanta Bhattacharjee, Ansuman Banerjee, Krishnendu Chakrabarty, Bhargab B. Bhattacharya:
Correctness Checking of Bio-chemical Protocol Realizations on a Digital Microfluidic Biochip. 504-509 - Pranab Roy, Samadrita Bhattacharya, Rupam Bhattacharyay, Firdousi Jamil Imam, Hafizur Rahaman, Parthasarathi Dasgupta:
A Novel Wire Planning Technique for Optimum Pin Utilization in Digital Microfluidic Biochips. 510-515
Session D4: Analog Circuits I
- Saurabh Kumar Singh, Nitin Bansal:
Output Impedance as Figure of Merit to Predict Transient Performance for Embedded Linear Voltage Regulators. 516-521 - Karthik Ramkumar Jeyashankar, Makrand Mahalley, Bharadwaj Amrutur:
A Time-Based Low Voltage Body Temperature Monitoring Unit. 522-527 - Hande Vinayak Gopal, Maryam Shojaei Baghini:
Trimless, PVT Insensitive Voltage Reference Using Compensation of Beta and Thermal Voltage. 528-533 - Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi:
A Low Power CMOS Imager Based on Distributed Compressed Sensing. 534-538
Session D5: Emerging Technologies
- Kamalika Datta, Indranil Sengupta:
All Optical Reversible Multiplexer Design Using Mach-Zehnder Interferometer. 539-544 - Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits. 545-550 - H. V. Jayashree, Himanshu Thapliyal, Vinod Kumar Agrawal:
Design of Dedicated Reversible Quantum Circuitry for Square Computation. 551-556 - P. Sai Phaneendra, Chetan Vudadha, Sreehari Veeramachaneni, M. B. Srinivas:
An Optimized Design of Reversible Quantum Comparator. 557-562
Session D6: Analog Circuits II
- Narla John Metilda Sagaya Mary, Ashis Maity, Amit Patra:
Light Load Efficiency Improvement in High Frequency DC-DC Buck Converter Using Dynamic Width Segmentation of Power MOSFET. 563-568 - Chithira Ravi, T. Rahul, Bibhudatta Sahoo:
Histogram Based Deterministic Digital Background Calibration for Pipelined ADCs. 569-574 - R. Gopikrishnan, Vijaya Sankara Rao Pasupureddi, Govindarajulu Regeti:
A Power Efficient Fully Differential Back Terminated Current-Mode HDMI Source. 575-579 - Makarand Shirasgaonkar, Roxanne Vu, Deborah Dressler, Nhat Nguyen, Kambiz Kaviani, Yueyong Wang:
An Adaptive Body-Biased Clock Generation System in 28nm CMOS. 580-583
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