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ORCIDComputer Architecture Letters, Volume 9
Volume 9, Number 1, January - June 2010
- Shruti R. Patil, David J. Lilja:
Using Resampling Techniques to Compute Confidence Intervals for the Harmonic Mean of Rate-Based Performance Metrics. 1-4 - André Seznec:
A Phase Change Memory as a Secure Main Memory. 5-8 - Seon-Yeong Park, Euiseong Seo, Ji-Yong Shin
, Seungryoul Maeng, Joonwon Lee:
Exploiting Internal Parallelism of Flash-based SSDs. 9-12 - Hari Subramoni, Fabrizio Petrini, Virat Agarwal, Davide Pasetto:
Intra-Socket and Inter-Socket Communication in Multi-core Systems. 13-16 - Giang Hoang, Chang Bae, Jack Lange, Lide Zhang, Peter A. Dinda, Russ Joseph:
A Case for Alternative Nested Paging Models for Virtualized Systems. 17-20 - Evgeni Krimer, Robert Pawlowski, Mattan Erez, Patrick Chiang:
Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications. 21-24 - Andrew D. Hilton, Amir Roth:
SMT-Directory: Efficient Load-Load Ordering for SMT. 25-28 - Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem:
A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors. 29-32 - Hyungjun Kim, Paul V. Gratz:
Leveraging Unused Cache Block Words to Reduce Power in CMP Interconnect. 33-36
Volume 9, Number 2, July - December 2010
- Kevin Skadron:
Editorial: Letter from the Editor-in-Chief. 37-44 - Syed Muhammad Zeeshan Iqbal, Yuchen Liang, Håkan Grahn:
ParMiBench - An Open-Source Benchmark for Embedded Multiprocessor Systems. 45-48 - Zhen Fang, Erik G. Hallnor, Bin Li, Mike Leddige, Seung Eun Lee, Donglai Dai, Srihari Makineni:
Boomerang: Reducing Power Consumption of Response Packets in NoCs with Minimal Performance Impact. 49-52 - Michael J. Lyons, Mark Hempstead, Gu-Yeon Wei, David M. Brooks:
The Accelerator Store framework for high-performance, low-power accelerator-based systems. 53-56 - Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter:
Centralized Adaptive Routing for NoCs. 57-60 - Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin:
Fractal Consistency: Architecting the Memory System to Facilitate Verification. 61-64
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