IEEE Design & Test of Computers, Volume 9

Volume 9, Number 1, January/March 1992

• News. 3-4

• Mani Soma: Guest Editor's Introduction: Mixing Analog and Digital Systems. 6-7
• Brian A. A. Antao, Arthur J. Brodersen:
  Techniques for Synthesis of Analog Integrated Circuits. 8-18
  
• Alvernon Walker, Winser E. Alexander, Parag K. Lala:
  Fault Diagnosis in Analog Circuits Using Element Modulation. 19-29
  
• Mustapha Slamani, Bozena Kaminska:
  Analog Circuit Fault Diagnosis Based on Sensitivity Computation and Functional Testing. 30-39
  
• William R. Simpson, John W. Sheppard:
  System Testability Assessment for Integrated Diagnostics. 40-54
  
• Don L. Millard, Karl R. Umstadter, Robert C. Block:
  Noncontact Testing of Circuits Via a Laser-Induced Plasma Electrical Pathway. 55-63
  
• Antonio Lloy:
  Advanced Fault Collapsing (Logic Circuits Testing). 64-71
  
• Ashish Pancholy, Janusz Rajski, Larry J. McNaughton:
  Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits. 72-83
  

• VLSI design. 95-

• TTTC Newsletter. 100-101

• DATC Newsletter. 102-103

Volume 9, Number 2, April/June 1992

• News. 2-3

• Allen Dewey: Guest Editor's Introduction: VHDL and Next-Generation Design Automation. 6-7
• Allen Dewey, Aart J. de Geus:
  VHDL: Toward a Unified View of Design. 8-17
  
• Jayanta Roy, Nand Kumar, Rajiv Dutta, Ranga Vemuri:
  DSS: A Distributed High-Level Synthesis System. 18-32
  
• Vijay Pitchumani, Pankaj Mayor, Nimish Radia:
  A VHDL Fault Diagnosis Tool Using Functional Fault Models. 33-41
  
• Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem:
  Formal Verification of VHDL Descriptions in the Prevail Environment. 42-56
  
• Vijay Nagasamy, Neerav Berry, Carlos Dangelo:
  Specification, Planning, and Synthesis in a VHDL Design Environment. 58-68
  
• Yaohan Chu, Donald L. Dietmeyer, James R. Duley, Fredrick J. Hill, Mario Barbacci, Charles W. Rose, Greg Ordy, Bill Johnson, Martin Roberts:
  Three Decades of HDLs: Part I, CDL Through TI-HDL. 69-81
  
• Colin Maunder:
  A D&T Special Report-Boundary Scan: An End-of-Term Report-IEEE Std 1149.1 Survey Results. 82-85
  

• Boundary-scan architecture, neutral testing models. 86-87

DATC Newsletter

• DATC Newsletter. 91-93

• TTTC Newsletter. 94-95

Volume 9, Number 3, July/September 1992

• Steven Trimberger: Guest Editor's Introduction: Field-Programmable Gate Arrays. 3-5
• Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar:
  DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. 7-20
  
• David E. van den Bout, Joseph N. Morris, Douglas Thomae, Scott Labrozzi, Scot Wingo, Peter Hallman:
  AnyBoard: An FPGA-Based, Reconfigurable System. 21-30
  
• Mani B. Srivastava, Robert W. Brodersen:
  Using VHDL for High-Level, Mixed-Mode System Simulation. 31-40
  
• John C. Willis, Daniel P. Siewiorek:
  Optimizing VHDL Compilation for Parallel Simulation. 42-53
  
• Dominique Borrione, Robert Piloty, Dwight D. Hill, Karl J. Lieberherr, Philip Moorby:
  Three Decades of HDLs: Part II, Conlan Through Verilog. 54-63
  
• John W. Sheppard, William R. Simpson:
  Applying Testability Analysis for Integrated Diagnostics. 65-78
  
• Bulent I. Dervisoglu:
  Boundary-Scan Update: IEEE P1149.2 Description and Status Report. 79-81
  
• A D&T Roundtable. 82-92

• DATC Newsletter. 93-94

• TTTC Newsletter. 95-96

Volume 9, Number 4, October/December 1992

• News. 2-3

• Yashwant K. Malaiya: Guest Editor's Introduction: VLSI Design 92. 4-5
• Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
  System Specification with the SpecCharts Language. 6-13
  
• Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh, Raja Venkateswaran:
  A Behavioral Fault Simulator for Ideal. 14-21
  
• Kewal K. Saluja, Chin-Foo See:
  An Efficient Signature Computation Method. 22-26
  
• Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
  Delay-Fault Diagnosis by Critical-Path Tracing. 27-32
  

• Zafar Hasan, David Harrison, Maciej J. Ciesielski:
  A Fast Partitioning Method for PLA-Based FPGAs. 34-39
  
• Steven H. Kelem, Jorge P. Seidel:
  Shortening the Design Cycle for Programmable Logic. 40-50
  
• David Marple:
  An MPGA-Like FPGA. 51-60
  

• Pat McHugh:
  IEEE P1149.5 Module Test and Maintenance Bus. 62-65
  
• A D&T Roundtable. 66-75
• 1992 Annual Index: Complete Subject/Author Listing. 76-79

• 1993 Editorial Calendar. 80-

• DATC Newsletter. 84-85

• TTTC Newsletter. 86-87

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