Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDJournal of Electronic Testing, Volume 16
Volume 16, Numbers 1-2, February 2000
- Vishwani D. Agrawal:
Editorial. 5 - Magdy S. Abadir:
Guest Editorial. 9-10 - Ta-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick:
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors. 13-27 - Pradip Bose:
Testing for Function and Performance: Towards an Integrated Processor Validation Methodology. 29-48 - Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen:
A Buffer-Oriented Methodology for Microarchitecture Validation. 49-65 - Jian Shen, Jacob A. Abraham:
An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation. 67-81 - Byeong Min, Gwan Choi:
Verification Simulation Acceleration Using Code-Perturbation. 83-90 - Jaehong Park, Carl Pixley, Michael Burns, Hyunwoo Cho:
An Efficient Logic Equivalence Checker for Industrial Circuits. 91-106 - Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz:
Automatic Vector Generation Using Constraints and Biasing. 107-120 - Li-C. Wang, Magdy S. Abadir:
On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors. 121-130 - Sandhya Seshadri, Michael S. Hsiao:
Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability. 131-145 - Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir:
Oscillation Ring Delay Test for High Performance Microprocessors. 147-155
Volume 16, Number 3, June 2000
- Vishwani D. Agrawal:
Editorial. 163 - Christian Landrault:
Guest Editorial. 167 - Gundolf Kiefer, Hans-Joachim Wunderlich:
Deterministic BIST with Partial Scan. 169-177 - Alfredo Benso, Silvia Cataldo, Silvia Chiusano
, Paolo Prinetto, Yervant Zorian:
A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures. 179-184 - A. Schubert, Walter Anheier:
On Random Pattern Testability of Cryptographic VLSI Cores. 185-192 - Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos:
Low Power BIST by Filtering Non-Detecting Vectors. 193-202 - Stefan Gerstendörfer, Hans-Joachim Wunderlich:
Minimized Power Consumption for Scan-Based BIST. 203-212 - Jaan Raik, Raimund Ubar:
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. 213-226 - Hans A. R. Manhaeve, Johan Verfaillie, B. Straka, J. P. Cornil:
Application of Supply Current Testing to Analogue Circuits, Towards a Structural Analogue Test Methodology. 227-234 - Rodrigo Picos, Miquel Roca, Eugeni Isern, Jaume Segura, Eugenio García-Moreno:
Experimental Results on BIC Sensors for Transient Current Testing. 235-241 - Toshiyuki Maeda, Kozo Kinoshita:
Compaction of IDDQ Test Sequence Using Reassignment Method. 243-249 - Anna Maria Brosa, Joan Figueras:
On Maximizing the Coverage of Catastrophic and Parametric Faults. 251-258 - Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand:
Combining Functional and Structural Approaches for Switched-Current Circuit Testing. 259-267 - Abdelhakim Khouas, Anne Derieux:
Fault Simulation for Analog Circuits Under Parameter Variations. 269-278 - Salvador Mir, Benoît Charlot, Bernard Courtois:
Extending Fault-Based Testing to Microelectromechanical Systems. 279-288 - Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. 289-299 - Harald P. E. Vranken:
Debug Facilities in the TriMedia CPU64 Architecture. 301-308
Volume 16, Number 4, August 2000
- Vishwani D. Agrawal:
Editorial. 315 - Michael S. Hsiao, Srimat T. Chakradhar:
Test Set Compaction Using Relaxed Subsequence Removal. 319-327 - Michael S. Hsiao, Srimat T. Chakradhar:
Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits. 329-338 - Claude Thibeault:
Diagnosis Method Using DeltaIDDQ Probabilistic Signatures: Theory and Results. 339-353 - Albrecht P. Stroele, Steffen Tarnick:
Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes. 355-367 - Jacob Savir:
Distributed BIST Architecture to Combat Delay Faults. 369-380 - Emil Gizdarski:
Detection of Delay Faults in Memory Address Decoders. 381-387 - Kanad Chakraborty, Pinaki Mazumder:
New March Tests for Multiport RAM Devices. 389-395
Volume 16, Number 5, October 2000
- Vishwani D. Agrawal:
Editorial. 403-404 - Serge N. Demidenko:
Guest Editorial. 407-408 - Bechir Ayari, Prab Varma:
Test Cycle Count Reduction in a Parallel Scan BIST Environment. 409-418 - Xiaowei Li, Paul Y. S. Cheung, Hideo Fujiwara:
LFSR-Based Deterministic TPG for Two-Pattern Testing. 419-426 - Chen-Huan Chiang, Sandeep K. Gupta:
BIST TPG for Combinational Cluster Interconnect Testing at Board Level. 427-442 - Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. 443-451 - Márta Rencz, Vladimír Székely, S. Török, Kholdoun Torki, Bernard Courtois:
IDDQ Testing of Submicron CMOS - by Cooling? 453-461 - Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi:
False-Path Removal Using Delay Fault Simulation. 463-476 - Huawei Li, Zhongcheng Li, Yinghua Min:
Reduction of Number of Paths to be Tested in Delay Testing. 477-485 - Said Hamdioui, Ad J. van de Goor:
Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy. 487-498 - Jian Liu, Rafic Z. Makki, Ayman I. Kayssi:
Dynamic Power Supply Current Testing of CMOS SRAMs. 499-511 - Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Testing the Local Interconnect Resources of SRAM-Based FPGA's. 513-520 - Surendra Bommu, Kiran B. Doreswamy, Srimat T. Chakradhar:
A Practical Vector Restoration Technique for Large Sequential Circuits. 521-539 - Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. 541-552 - Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara:
A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency. 553-566
Volume 16, Number 6, December 2000
- Vishwani D. Agrawal:
Editorial. 571 - Hussain Al-Asaad, John P. Hayes:
Logic Design Validation via Simulation and Automatic Test Pattern Generation. 575-589 - John Marty Emmert, Dinesh K. Bhatia:
A Fault Tolerant Technique for FPGAs. 591-606 - Cecilia Metra, Jien-Chung Lo:
Intermediacy Prediction for High Speed Berger Code Checkers. 607-615 - Michele Favalli, Cecilia Metra:
Bridging Faults in Pipelined Circuits. 617-629 - André Ivanov, Vikram Devdas:
Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study. 631-634 - Charles E. Stroud, James R. Bailey, Johan R. Emmert:
A New Method for Testing Re-Programmable PLAs. 635-640
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-18 20:20 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
