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ORCIDJournal of Electronic Testing, Volume 24
Volume 24, Numbers 1-3, June 2008
- Vishwani D. Agrawal:
Editorial. 1 - Nur A. Touba, Adelio Salsano, Minsu Choi:
Guest Editorial. 9-10 - Yoichi Sasaki, Kazuteru Namba, Hideo Ito:
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. 11-19 - Mahdi Fazeli
, Reza Farivar, Seyed Ghassem Miremadi:
Error Detection Enhancement in PowerPC Architecture-based Embedded Processors. 21-33 - Cristiana Bolchini, Antonio Miele, Fabio Rebaudengo, Fabio Salice, Donatella Sciuto, Luca Sterpone, Massimo Violante:
Software and Hardware Techniques for SEU Detection in IP Processors. 35-44 - Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante:
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs. 45-56 - Rui Gong, Wei Chen, Fang Liu, Kui Dai, Zhiying Wang:
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique. 57-65 - Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Cristian Grecu:
Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding. 67-81 - Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Lima Kastensmidt, Luigi Carro:
Majority Logic Mapping for Soft Error Dependability. 83-92 - Daniele Rossi, Martin Omaña, Cecilia Metra:
Checkers' No-Harm Alarms and Design Approaches to Tolerate Them. 93-103 - Salvatore Pontarelli, Marco Ottavi, Vamsi Vankamamidi, Gian Carlo Cardarilli, Fabrizio Lombardi, Adelio Salsano:
Analysis and Evaluations of Reliability of Reconfigurable FPGAs. 105-116 - Joonhyuk Yoo, Manoj Franklin:
Hierarchical Verification for Increasing Performance in Reliable Processors. 117-128 - Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka:
Performance-Optimized Design for Parametric Reliability. 129-141 - Shambhu J. Upadhyaya, Nandakumar P. Venugopal, Nihal Shastry, Srinivasan Gopalakrishnan, Bharath V. Kuppuswamy, Rana Bhowmick, Prerna Mayor:
Design Considerations for High Performance RF Cores Based on Process Variation Study. 143-155 - Kristian Granhaug, Snorre Aunet:
Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy. 157-163 - Lushan Liu, Pradeep Nagaraj, Shambhu J. Upadhyaya, Ramalingam Sridhar:
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs. 165-179 - Da-Ming Chang, Jin-Fu Li, Yu-Jen Huang:
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy. 181-192 - Xiaojun Ma, Fabrizio Lombardi:
Substrate Testing on a Multi-Site/Multi-Probe ATE. 193-201 - Kyriakos Christou, Maria K. Michael, Spyros Tragoudas:
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation. 203-222 - Yukiya Miura, Jiro Kato:
Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and X - Y Zoning Method. 223-233 - Sverre Wichlund, Frank Berntsen, Einar J. Aas:
Scan Test Response Compaction Combined with Diagnosis Capabilities. 235-246 - Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi:
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving. 247-257 - Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty:
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs. 259-269 - Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi:
Monomer Control for Error Tolerance in DNA Self-Assembly. 271-284 - Lei Fang, Michael S. Hsiao:
Bilateral Testing of Nano-scale Fault-Tolerant Circuits. 285-296 - Xiaojun Ma, Jing Huang, Cecilia Metra, Fabrizio Lombardi:
Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA. 297-311 - Myungsu Choi, Minsu Choi:
Scalability of Globally Asynchronous QCA (Quantum-Dot Cellular Automata) Adder Design. 313-320
Volume 24, Number 4, August 2008
- Vishwani D. Agrawal:
Editorial. 321 - Nicola Nicolici, Patrick Girard:
Guest Editorial. 325-326 - Xijiang Lin, Yu Huang:
Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells. 327-334 - Ozgur Sinanoglu:
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations. 335-351 - Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault:
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. 353-364 - Hong-Sik Kim, Sungho Kang, Michael S. Hsiao:
A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment. 365-378 - Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. 379-391 - Ho Fai Ko, Nicola Nicolici:
Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy. 393-403 - Ashesh Rastogi, Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu:
On Composite Leakage Current Maximization. 405-420
Volume 24, Number 5, October 2008
- Vishwani D. Agrawal:
Editorial. 421 - Egas Henes Neto, Gilson I. Wirth, Fernanda Lima Kastensmidt:
Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors. 425-437 - Ozgur Sinanoglu:
Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells. 439-448 - Xinsong Zhang, Simon S. Ang, Chandra Carter:
Comparison of NIST and Wavelet Transform Test Point Selection Methods For a Programmable Gain Amplifier. 449-460 - Stephen K. Sunter, Aubin Roy:
Noise-Insensitive Digital BIST for any PLL or DLL. 461-472 - Guangyu Huang, Cher Ming Tan:
Reverse Breakdown Voltage Measurement for Power P+NN+ Rectifier. 473-479 - Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu:
Controllability of Static CMOS Circuits for Timing Characterization. 481-496 - Erik Larsson, Zebo Peng:
A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling. 497-504
Volume 24, Number 6, December 2008
- Vishwani D. Agrawal:
Editorial. 505-506 - Steffen Tarnick:
Self-Testing Embedded Borden t -UED Code Checkers for t = 2 k q - 1 with q = 2 m - 1. 509-527 - Roberto Gómez, Alejandro Girón, Víctor H. Champac:
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines. 529-538 - Mariagrazia Graziano, Massimo Ruo Roch:
An Automotive CD-Player Electro-Mechanics Fault Simulation Using VHDL-AMS. 539-553 - Norbert Dumas, Zhou Xu, Kostas Georgopoulos, R. John T. Bunyan, Andrew Richardson:
Online Testing of MEMS Based on Encoded Stimulus Superposition. 555-566 - Shalabh Goyal, Abhijit Chatterjee:
Linearity Testing of A/D Converters Using Selective Code Measurement. 567-576 - Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy:
Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. 577-590 - Myung-Hoon Yang, YongJoon Kim, Sunghoon Chun, Sungho Kang:
An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR. 591-595
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