IET Computers & Digital Techniques, Volume 3
Volume 3, Number 1, January 2009
Irith Pomeranz, Sudhakar M. Reddy: Definition and generation of partially-functional broadside tests. 1-13- Ya-shuai Lü, Li Shen, Libo Huang, Zhiying Wang, Nong Xiao: Optimal subgraph covering for customisable VLIW processors. 14-23
- Ian D. L. Anderson, Mohammed A. S. Khalid: SC Build: a computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gate arrays. 24-32
- George Theodoridis, Nikolaos Vassiliadis, Spiridon Nikolaidis: An integer linear programming model for mapping applications on hybrid systems. 33-42
- Yi-Hsin Wu, Cheng-Juei Yu, Sheng-De Wang: Heuristic algorithm for the resource constrained scheduling problem during high-level synthesis. 43-51
- Benjamin Carrión Schäfer, Taewhan Kim: Autonomous temperature control technique in VLSI circuits through logic replication. 62-71
- Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung: Hardware architectures for eigenvalue computation of real symmetric matrices. 72-84
- Irith Pomeranz, Sudhakar M. Reddy: Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution. 85-93
- Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic: HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors. 94-108
- Athanasios Milidonis, Vasileios Porpodas, Nikolaos Alachiotis, Athanasios P. Kakarountas, Harris E. Michail, George A. Panagiotakopoulos, Costas E. Goutis: Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse. 109-123
- Jonathan Phillips, Arvind Sudarsanam, Harikrishna Samala, Ramachandra Kallam, J. Carver, Aravind Dasu: Methodology to derive context adaptable architectures for FPGAs. 124-141
Volume 3, Number 2, March 2009
- Aiman H. El-Maleh, Mustafa Imran Ali, Ahmad A. Al-Yamani: Reconfigurable broadcast scan compression using relaxation-based test vector decomposition. 143-161
- Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim: Interconnect and communication synthesis for distributed register-file microarchitecture. 162-174
- Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya: Droop sensitivity of stuck-at fault tests. 175-193
- Shijun Lin, Li Su, Haibo Su, Guofei Zhou, Depeng Jin, Lieguang Zeng: Design networks-on-chip with latency/ bandwidth guarantees. 184-194
- Ozgur Sinanoglu, Mohammed Al-Mulla, Mohammed Nael Taha: Utilisation of inverse compatibility for test cost reductions. 195-204
- Nikolas Kroupis, Dimitrios Soudris: High-level estimation methodology for designing the instruction cache memory of programmable embedded platforms. 205-221
- Irith Pomeranz, Sudhakar M. Reddy: Test vector chains for increasing the fault coverage and numbers of detections. 222-233
Volume 3, Number 3, May 2009
- Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems. 235-246
- Jacqueline E. Rice, Kenneth B. Kent: Case studies in determining the optimal field programmable gate array design for computing highly parallelisable problems. 247-258
- Rastislav J. R. Struharik, Ladislav A. Novak: Intellectual property core implementation of decision trees. 259-269
- Frank P. Burns, Julian P. Murphy, Albert Koelmans, Alexandre Yakovlev: Efficient advanced encryption standard implementation using lookup and normal basis. 270-280
- Jimson Mathew, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan: Single error correctable bit parallel multipliers over GF(2m). 281-288
- Mahdi Fazeli, Seyed Ghassem Miremadi, Alireza Ejlali, Ahmad Patooghy: Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies. 289-303
- F.-M. Wang, W.-C. Wang, James Chien-Mo Li: Time-space test response compaction and diagnosis based on BCH codes. 304-313
Volume 3, Number 4, July 2009
- Irith Pomeranz, Sudhakar M. Reddy: Test compaction methods for transition faults under transparent-scan. 315-328
- Chichyang Chen: Error analysis of LNS addition/subtraction with direct-computation implementation. 329-337
- Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke: Advanced verification by automatic property generation. 338-353
- Ahmet Onur Durahim, Erkay Savas, Berk Sunar, Thomas Brochmann Pedersen, Övünç Kocabas: Transparent code authentication at the processor level. 354-372
- Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk: High-throughput one-dimensional median and weighted median filters on FPGA. 384-394
Volume 3, Number 5, September 2009
- Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij: Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis. 398-412
- Maurizio Palesi, Shashi Kumar, Vincenzo Catania: Bandwidth-aware routing algorithms for networks-on-chip platforms. 413-429
- Masoud Daneshtalab, Masoumeh Ebrahimi, Siamak Mohammadi, Ali Afzali-Kusha: Low-distance path-based multicast routing algorithm for network-on-chips. 430-442
- Samuel Rodrigo, Simone Medardoni, José Flich, Davide Bertozzi, José Duato: Efficient implementation of distributed routing algorithms for NoCs. 460-475
- Jaan Raik, Vineeth Govind, Raimund Ubar: Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. 476-486
- Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach: Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application. 487-500
- Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete: Impact of on-chip network parameters on nuca cache performances. 501-512
- Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, Hoi-Jun Yoo: Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor. 513-524
- Sílvio R. F. de Fernandes, Bruno Cruz de Oliveira, M. Costa, Ivan Saraiva Silva: Processing while routing: a network-on-chipbased parallel system. 525-538
- Erno Salminen, Cristian Grecu, Timo D. Hämäläinen, André Ivanov: Application modelling and hardware description for network-on-chip benchmarking. 539-550
Volume 3, Number 6, November 2009
- Bipul C. Paul, Krishnendu Chakrabarty: Advances in nanoelectronics circuits and systems [Editorial]. 551-552
- Vincent Mao, V. Thusu, Chris Dwyer, Krishnendu Chakrabarty: Connecting fabrication defects to fault models and SPICE simulations for DNA self-assembled nanoelectronics. 553-569
- Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki, Farhan Khan: Defect-tolerant n2-transistor structure for reliable nanoelectronic designs. 570-580
- Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Is triple modular redundancy suitable for yield improvement? 581-592
- Hamed F. Dadgour, Kaustav Banerjee: Hybrid NEMS-CMOS integrated circuits: A novel strategy for energy-efficient designs. 593-608
- Rajat Subhra Chakraborty, Somnath Paul, Yu Zhou, Swarup Bhunia: Low-power hybrid complementary metaloxide- semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping. 609-624
- Benjamin Gojman, Harika Manem, Garrett S. Rose, André DeHon: Inversion schemes for sublithographic programmable logic arrays. 625-642
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last updated on 2013-06-18T211851 by the dblp team