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ORCIDIntegration, Volume 12
Volume 12, Number 1, November 1991
- Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer:
Scheduling under resource constraints and module assignment. 1-19 - Daniel Boley, Franklin T. Luk:
A well conditioned checksum scheme for algorithmic fault tolerance. 21-32 - Josef G. Krammer, Ernst G. Bernard, Matthias Sauer, Josef A. Nossek:
Sorting on defective VLSI-arrays. 33-48 - Heming Chan, Pinaki Mazumder, Khushro Shahookar:
Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome. 49-77 - Erik Paaske, Steen Pedersen, Jens Sparsø:
An area-efficient path memory structure for VLSI implementation of high speed Viterbi decoders. 79-91 - David H. K. Hoe, C. André T. Salama:
GaAs pipelined dynamic logic. 93-105
Volume 12, Number 2, December 1991
- Srinivas Devadas, Kurt Keutzer:
An automata-theoretic approach to behavioral equivalence. 109-129 - David C. Ku, Giovanni De Micheli:
Constrained resource sharing and conflict resolution in Hebe. 131-165 - Lothar Thiele:
On the analysis and optimization of selftimed processor arrays. 167-187 - Ioannis G. Tollis:
Wiring in uniform grids and two-colorable maps. 189-210 - Tom A. M. Kevenaar, Domine M. W. Leenaerts:
A flexible hierarchical piecewise linear simulator. 211-235
Volume 12, Number 3, December 1991
- Farhad Mavaddat, M. Mahmood:
On compiling behaviour to silicon: a formal language approach. 239-266 - David Springer, D. E. Thomas:
New methods for coloring and clique partitioning in data path allocation. 267-292 - Alain Darte:
Regular partitioning for synthesizing fixed-size systolic arrays. 293-304 - Joseph F. JáJá:
Parallel algorithms for VLSI routing. 305-320 - Michael R. Fellows
, Michael A. Langston:
Fast search algorithms for layout permutation problems. 321-337 - Michael Kaufmann, Paul Molitor:
Minimal stretching of a layout to ensure 2-layer wirability. 339-352
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