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ORCIDIntegration, Volume 2
Volume 2, Number 1, March 1984
- Ole Olesen, Christer Svensson:
NORCHIP, a silicon brokers model. 3-13 - Armin B. Cremers, Sun-Yuan Kung:
On programming VLSI concurrent array processors. 15-26 - Qingjian Yu, Omar Wing:
PLMAP - A piecewise linear MOS circuit analysis program. 27-48 - Dag Svanæs, Einar J. Aas:
Test generation through logic programming. 49-67
Volume 2, Number 2, June 1984
- Lambert Spaanenburg:
Editorial. 83 - N. P. van der Meijs, J. T. Fokkema:
VLSI circuit reconstruction from mask topology. 85-119 - L. Silvestri, S. Garue, Mario Marchente:
An heuristic SPICE2-based approach for 2D IIL device simulation. 121-132 - Giuseppe Alia, Ferruccio Barsi, Enrico Martinelli:
A fast near optimum VLSI implementation of FFT using residue number systems. 133-147 - Rudolf H. Mak:
Optimization of programmable logic arrays. 149-162 - Kurt Mehlhorn:
AT2-optimal VLSI integer division and integer square rooting. 163-167
Volume 2, Number 3, September 1984
- Lambert Spaanenburg:
Editorial. 189 - Magdy A. Bayoumi, Graham A. Jullien, William C. Miller:
A VLSI model for residue number system architectures. 191-211 - N. H. C. Yung, C. R. Allen, Hans K. E. Liesenberg, D. J. Kinniment:
A recursive design methodology for VLSI: Theory and example. 213-225 - David P. LaPotin, Sani R. Nassif, Jayanth V. Rajan, Michael L. Bushnell, John A. Nestor:
DIF: A framework for VLSI multi-level representation. 227-241 - Claudio Moraga:
On a case of symbiosis between systolic arrays. 243-253
Volume 2, Number 4, December 1984
- Lambert Spaanenburg:
Editorial. 277 - Martine D. F. Schlag, Lin S. Woo, Chak-Kuen Wong:
Maximizing pin alignment by pin permutations. 279-307 - Kewal K. Saluja, Kim Thang Le:
Testable design of large random access memories. 309-330 - Kjell Øystein Arisland, Anne Cathrine Aasbø, Are Nundal:
VLSI parallel shift sort algorithm and design. 331-347 - L. N. M. Edward:
On improving the quality of simple graphics. 349-355
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