Volume 43, Number 1, January 2010
, Guangsheng Ma
, Shu Zhang
: Formal verification of high-level data-flow synthesis designs using relational modeling and symbolic computation.
: Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2m).
Volume 43, Number 2, April 2010
, Sheldon X.-D. Tan
: Statistical analysis of large on-chip power grid networks by variational reduction scheme.
: Reducing signal timing variations in inter-core busses.
Volume 43, Number 3, June 2010
: Logical effort based dynamic power estimation and optimization of static CMOS circuits.
, Jin Shi
, Shuai Li
: Optimization of via distribution and stacked via in multi-layered P/G networks.
Volume 43, Number 4, September 2010
, Sheqin Dong
, Yuchun Ma
: Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs.
, Takeshi Yoshimura
: Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints.