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ORCIDIPSJ Transactions on System LSI Design Methodology, Volume 2
Volume 2, February 2009
- Hidetoshi Onodera:
Message from the Editor-in-Chief. 1 - Masahiro Fujita:
Trends in Formal Verification Techniques for C-based Hardware Designs. 2-17 - Makoto Takamiya, Takayasu Sakurai:
Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering. 18-29 - Liangwei Ge, Song Chen
, Takeshi Yoshimura:
Exploration of Schedule Space by Random Walk. 30-42 - Sho Kodama, Yusuke Matsunaga:
Binding Refinement for Multiplexer Reduction. 43-52 - Kazuhito Ito, Hidekazu Seto:
Reducing Power Dissipation of Data Communications on LSI with Scheduling Exploration. 53-63 - Naohiro Hamada, Yuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya:
A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation. 64-79 - Sho Takeuchi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Checker Generation of Assertions with Local Variables for Model Checking. 80-92 - Ryosuke Inagaki, Norio Sadachika, Dondee Navarro, Mitiko Miura-Mattausch, Yasuaki Inoue:
A GIDL-Current Model for Advanced MOSFET Technologies without Binning. 93-102 - Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura:
An Asynchronous IEEE-754-standard Single-precision Floating-point Divider for FPGA. 103-113 - Xianghui Wei, Takeshi Ikenaga, Satoshi Goto:
A Low Bandwidth Integer Motion Estimation Module for MPEG-2 to H.264 Transcoding. 114-121 - Wen Ji, Xing Li, Takeshi Ikenaga, Satoshi Goto:
A High Throughput LDPC Decoder Design Based on Novel Delta-value Message-passing Schedule. 122-130 - Sudipta Kundu, Sorin Lerner, Rajesh Gupta:
High-Level Verification. 131-144 - Yao-Wen Chang, Zhe-Wei Jiang, Tung-Chieh Chen:
Essential Issues in Analytical Placement Algorithms. 145-166 - Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada:
A Generalized Framework for Energy Savings in Hard Real-Time Embedded Systems. 167-179 - Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada:
Partitioning and Allocation of Scratch-Pad Memory in Priority-Based Multi-Task Systems. 180-188 - Seiichiro Yamaguchi, Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura:
Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion. 189-199 - Taiga Takata, Yusuke Matsunaga:
Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs. 200-211 - Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga:
Framework for Parallel Prefix Adder Synthesis Considering Switching Activities. 212-221 - Qing Dong, Shigetoshi Nakatake:
Structured Placement with Topological Regularity Evaluation. 222-238 - Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura:
An Optimization Technique for Low-Energy Embedded Memory Systems. 239-249 - Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. 250-262 - Yiqing Huang, Qin Liu, Takeshi Ikenaga:
Macroblock Feature Based Adaptive Propagate Partial SAD Architecture for HDTV Application. 263-273
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