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ORCIDIPSJ Transactions on System LSI Design Methodology, Volume 3
Volume 3, February 2010
- Hidetoshi Onodera:
Message from the Editor-in-Chief. 1 - Jason Cong, Guojie Luo:
Advances and Challenges in 3D Physical Design. 2-18 - Kwang-Ting (Tim) Cheng
, Hsiu-Ming (Sherman) Chang:
Recent Advances in Analog, Mixed-Signal, and RF Testing. 19-46 - Shouhei Nomoto, Shorin Kyo, Shin'ichiro Okazaki:
Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application. 47-56 - Kenshu Seto, Masahiro Fujita:
Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands. 57-68 - Takeshi Matsumoto, Tasuku Nishihara, Masahiro Fujita:
Performance Estimation with Automatic False-Path Detection for System-Level Designs. 69-80 - Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura:
Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems. 81-90 - Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi:
High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor. 91-104 - Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara:
Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic. 105-117 - Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators. 118-129 - Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera:
Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells. 130-139 - Björn Sander, Andreas Bernauer, Wolfgang Rosenstiel:
Design and Run-time Reliability at the Electronic System Level. 140-160 - Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura:
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP). 161-178 - Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation. 179-193 - Arif Ullah Khan, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda:
A Unified Performance Estimation Method for Hardware and Software Components in Multiprocessor System-On-Chips. 194-206 - Takahiro Kumura, Soichiro Taga, Nagisa Ishiura, Yoshinori Takeuchi, Masaharu Imai:
Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors. 207-221 - Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions. 222-233 - Benjamin Carrión Schäfer, Majid Sarrafzadeh:
Semi-Automatic Control Unit Generation for Complex VLSI Designs. 234-243 - Hideki Yamada, Yui Ogawa, Tomonori Ooya, Tomoya Ishimori, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri:
Automatic Pipeline Construction Focused on Similarity of Rate Law Functions for an FPGA-based Biochemical Simulator. 244-256 - Hidekazu Seto, Kazuhito Ito:
A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI. 257-267 - Kiyoharu Hamaguchi, Kazuya Masuda, Toshinobu Kashiwabara:
Approximate Model Checking Using a Subset of First-order Logic. 268-282 - Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen:
On Delay Test Quality for Test Cubes. 283-291 - Zhixiang Chen, Xiongxin Zhao, Xiao Peng, Dajiang Zhou, Satoshi Goto:
A High Parallelism LDPC Decoder with an Early Stopping Criterion for WiMax and WiFi Application. 292-302 - Xun He, Dajiang Zhou, Jinjia Zhou, Satoshi Goto:
High Profile Intra Prediction Architecture for UHD H.264 Decoder. 303-313
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