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ORCIDMicroprocessors and Microsystems - Embedded Hardware Design, Volume 32
Volume 32, Number 1, February 2008
- Gabriela Peretti
, Eduardo Romero, Carlos A. Marqués:
Testing digital low-pass filters using oscillation-based test. 1-9 - Farshad Safaei, Ahmad Khonsari, Mahmood Fathy, Mohamed Ould-Khaoua:
Performance modelling of pipelined circuit switching in hypercubes with hot spot traffic. 10-22 - Iván González, Sergio López-Buedo, Francisco J. Gomez-Arribas:
Implementation of secure applications in self-reconfigurable systems. 23-32 - Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero:
A hardware design of a massive-parallel, modular NN-based vector quantizer for real-time video coding. 33-44 - Andrzej Chydzinski, Ryszard Winiarczyk:
On the blocking probability in batch Markovian arrival queues. 45-52
Volume 32, Number 2, March 2008
- Paolo Zicari, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo:
A matrix product accelerator for field programmable systems on chip. 53-67 - Armando Mora Campos, Francisco José Ballester-Merelo, Marcos Martínez Peiró, José A. Canals Esteve:
Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management. 68-78 - Byung-Soo Choi, Jun-Dong Cho:
Partial resolution for redundant operation table. 79-94 - John A. Kalomiros, John N. Lygouras:
Design and evaluation of a hardware/software FPGA-based system for fast image processing. 95-106 - Shubhajit Roy Chowdhury, Dipankar Chakrabarti, Hiranmay Saha:
FPGA realization of a smart processing system for clinical diagnostic applications using pipelined datapath architectures. 107-120
Volume 32, Number 3, May 2008
- Mehdi Kargahi, Ali Movaghar:
Stochastic DVS-based dynamic power management for soft real-time systems. 121-144 - Maurelio Boari, Enrico Lodolo, Stefano Monti, Samuele Pasini:
Middleware for automatic dynamic reconfiguration of context-driven services. 145-158 - Christos Georgoulas, Leonidas G. Kotoulas, Georgios Ch. Sirakoulis, Ioannis Andreadis, Antonios Gasteratos:
Real-time disparity map computation module. 159-170 - Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras:
Asymmetrically banked value-aware register files for low-energy and high-performance. 171-182
Volume 32, Number 4, June 2008
- Md. Mafijul Islam, Magnus Själander, Per Stenström:
Early detection and bypassing of trivial operations to improve energy efficiency of processors. 183-196 - Itziar Marín, Jagoba Arias, E. Arceredillo, Aitzol Zuloaga, Iker Losada, Jon Mabe:
LL-MAC: A low latency MAC protocol for wireless self-organised networks. 197-209 - Janardhan Singaraju, John A. Chandy:
FPGA based string matching for network processing applications. 210-222 - Hamid Fadishei, Mehdi Saeedi, Morteza Saheb Zamani:
A fast IP routing lookup architecture for multi-gigabit switching routers based on reconfigurable systems. 223-233 - Wei Hu, Yongxin Zhu, Zonghua Gu, Lei Jiang:
Pre-synthesis resource generation and estimation for transport-triggered architecture (TTA)-like architecture. 234-242
Volume 32, Numbers 5-6, August 2008
- Hana Kubátová:
Dependability and testing of modern digital systems. 243 - David Roberts, Nam Sung Kim, Trevor N. Mudge:
On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology. 244-253 - Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar:
Hybrid BIST optimization using reseeding and test set compaction. 254-262 - Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler:
On the construction of small fully testable circuits with low depth. 263-269 - Silvio Misera, Heinrich Theodor Vierhaus, André Sieber:
Simulated fault injections and their acceleration in SystemC. 270-278 - Raimund Ubar, Sergei Kostin, Jaan Raik:
Embedded fault diagnosis in digital systems with BIST. 279-287 - Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi:
Graph based test case generation for TLM functional verification. 288-295 - Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman:
Testability analysis based on the identification of testable blocks with predefined properties. 296-302 - Andrzej Krasniewski:
Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAs. 303-312 - Volker Hampel, Peter Sobe, Erik Maehle:
Experiences with a FPGA-based Reed/Solomon-encoding coprocessor. 313-320 - Kalle Holma, Mikko Setälä, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen:
Evaluating the model accuracy in automated design space exploration. 321-329 - Alex Janek, Christoph Trummer, Christian Steger, Reinhold Weiss, Josef Preishuber-Pfluegl, Markus Pistauer:
Simulation based verification of energy storage architectures for higher class tags supported by energy harvesting devices. 330-339 - Petr Fiser, Hana Kubátová:
Column-matching based mixed-mode test pattern generator design technique for BIST. 340-350
Volume 32, Number 7, October 2008
- Qingfeng Zhuge, Chun Jason Xue, Meikang Qiu, Jingtong Hu, Edwin Hsing-Mean Sha:
Timing optimization via nest-loop pipelining considering code size. 351-363 - Maziar Goudarzi, Shaahin Hessabi, Naser MohammadZadeh, Nasim Zainolabedini:
The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model. 364-374 - Hui Wang, Rama Sangireddy:
Streamlining long latency instructions for seamlessly combined out-of-order and in-order execution. 375-385 - Ming Z. Zhang, Ming-Jung Seow, Li Tao, Vijayan K. Asari:
A tunable high-performance architecture for enhancement of stream video captured under non-uniform lighting conditions. 386-393 - Ismail Kadayif, Ayhan Zorlubas, Selcuk Koyuncu, Olcay Kabal, Davut Akcicek, Yucel Sahin, Mahmut T. Kandemir:
Capturing and optimizing the interactions between prefetching and cache line turnoff. 394-404 - Fadi N. Sibai:
On the performance benefits of sharing and privatizing second and third-level cache memories in homogeneous multi-core architectures. 405-412
Volume 32, Number 8, November 2008
- Xiaorui Wang, Chenyang Lu, Christopher D. Gill:
FCS/nORB: A feedback control real-time scheduling service for embedded ORB middleware. 413-424 - Roger Kahn, Shlomo Weiss:
Thrifty BTB: A comprehensive solution for dynamic power reduction in branch target buffers. 425-436 - Paolo Zicari, Emanuele Sciagura, Stefania Perri, Pasquale Corsonello:
A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals. 437-446 - Jan Krakora, Zdenek Hanzálek:
FPGA based tester tool for hybrid real-time systems. 447-459 - Eduardo Tavares, Paulo Romero Martins Maciel, Bruno Silva:
Modeling hard real-time systems considering inter-task relations, dynamic voltage scaling and overheads. 460-473
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