Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSIGARCH Computer Architecture News, Volume 38
Volume 38, Number 1, March 2010
- James C. Hoe, Vikram S. Adve:
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010. ACM 2010, ISBN 978-1-60558-839-1 [contents]
Volume 38, Number 2, May 2010
- Alexander Thomasian:
Storage research in industry and universities. 1-48 - Wolfgang Matthes:
Resources instead of cores? 49-63
- Mark Thorson:
Internet nuggets. 64-67
Volume 38, Number 3, June 2010
- André Seznec, Uri C. Weiser, Ronny Ronen:
37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France. ACM 2010, ISBN 978-1-4503-0053-7 [contents]
Volume 38, Number 4, September 2010
- Marco Aurelio Nuño-Maganda, César Torres-Huitzil:
A temporal coding hardware implementation for spiking neural networks. 2-7 - Hirokazu Morishita, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system. 8-13 - Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk:
Efficient reconfigurable design for pricing asian options. 14-20 - Tadayoshi Horita, Itsuo Takanami:
An FPGA-based fast classifier with high generalization property. 21-26 - Andrew Putnam, Aaron Smith, Doug Burger:
Dynamic vectorization in the E2 dynamic multicore architecture. 27-32 - Jong Kyung Paek, Kiyoung Choi, Jong-eun Lee:
Binary acceleration using coarse-grained reconfigurable architecture. 33-39 - Keisuke Dohi, Yuichiro Shibata, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri, Duncan A. Buell:
Implementation of a programming environment with a multithread model for reconfigurable systems. 40-45 - Mojtaba Sabeghi, Hamid Mushtaq, Koen Bertels:
Runtime multitasking support on polymorphic platforms. 46-52 - Kuen Hung Tsoi, Anson H. T. Tse, Peter R. Pietzuch, Wayne Luk:
Programming framework for clusters with heterogeneous accelerators. 53-59 - Claude Tadonki, Gilbert Grosdidier, Olivier Pène:
An efficient CELL library for lattice quantum chromodynamics. 60-65 - Ryan Taylor, Xiaoming Li:
Software-based branch predication for AMD GPUs. 66-72 - Sebastian Banescu, Florent de Dinechin, Bogdan Pasca
, Radu Tudoran:
Multipliers for floating-point double precision and beyond on FPGAs. 73-79 - Kentaro Sano, Luzhou Wang, Satoru Yamamoto:
Prototype implementation of array-processor extensible over multiple FPGAs for scalable stencil computation. 80-86 - Chi Chiu Tsang, Hayden Kwok-Hay So:
Dynamic power reduction of FPGA-based reconfigurable computers using precomputation. 87-92
- Mark Thorson:
Internet nuggets. 93-96
Volume 38, Number 5, December 2010
- Manideepa Mukherjee, Amitabha Sinha:
A novel architecture for conversion of binary to single digit double base numbers. 1-6 - Shobha T, Syed Akram, G. Varaprasad:
Design and development of framework for diagnosing intermediate nodes. 7-11 - Fuad Tabba:
Adding concurrency in python using a commercial processor's hardware transactional memory support. 12-19 - Alexander Thomasian:
Why specialized disks for composite operations may be unnecessary. 20-27
- Mark Thorson:
Internet nuggets. 28-36
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-18 20:21 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
