Volume 7, Number 1, April 2010
- Xiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu:
A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints.
- Zhong-Ho Chen, Alvin Wen-Yu Su:
A hardware/software framework for instruction and data scratchpad memory allocation.
- Dong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, Hsien-Hsin S. Lee:
Chameleon: Virtualizing idle acceleration cores of a heterogeneous multicore processor for caching and prefetching.
- Daniel Sanchez, George Michelogiannakis, Christos Kozyrakis:
An analysis of on-chip interconnection networks for large-scale chip multiprocessors.
- Xiuyi Zhou, Jun Yang, Marek Chrobak, Youtao Zhang:
Performance-aware thermal management via task scheduling.
Volume 7, Number 2, September 2010
- Arun Raghavan, Colin Blundell, Milo M. K. Martin:
Token tenure and PATCH: A predictive/adaptive token-counting hybrid.
- Christian Wimmer, Hanspeter Mössenböck:
Automatic feedback-directed object fusing.
- Benjamin C. Lee, David Brooks:
Applied inference: Case studies in microarchitectural design.
- Ryan Rakvic, Qiong Cai, José González, Grigorios Magklis, Pedro Chaparro, Antonio González:
Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors.
- Derek Chi-Wai Pao, Wei Lin, Bin Liu:
A memory-efficient pipelined implementation of the aho-corasick string-matching algorithm.
- Xuejun Yang, Ying Zhang, Xicheng Lu, Jingling Xue, Ian Rogers, Gen Li, Guibin Wang, Xudong Fang:
Exploiting the reuse supplied by loop-dependent stream references for stream processors.
- Vijay Janapa Reddi, Simone Campanoni, Meeta Sharma Gupta, Michael D. Smith, Gu-Yeon Wei, David Brooks, Kim M. Hazelwood:
Eliminating voltage emergencies via software-guided code transformations.
Volume 7, Number 3, December 2010
- Qin Zhao, Ioana Cutcutache, Weng-Fai Wong:
PiPA: Pipelined profiling and analysis on multicore systems.
13
- Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer:
Quality of service shared cache management in chip multiprocessor architecture.
14
- Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ramakrishnan Rajamony, Yuan Xie:
Design exploration of hybrid caches with disparate memory technologies.
15
- Kornilios Kourtis, Georgios I. Goumas, Nectarios Koziris:
Exploiting compression opportunities to improve SpMxV performance on shared memory systems.
16
Volume 7, Number 4, December 2010
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